A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

Claims

20 · 2 independent · depth 4

20 granted claims

›1.independentA method for making an integrated circuit package, the method comprising:nproviding a handle wafer having a first region and a second region, the firs…+12

›2.↳ 1The method of claim 1, wherein the other one of the electroconductive pads of the handle wafer is disposed on an upper surface thereof.d2

›3.↳ 1The method of claim 1, wherein the forming of the capacitor comprises:nmaking a recess in a lower surface of the first region, the recess having an in…d2+5

›9.↳ 1The method of claim 1, wherein a volume is defined between the semiconductor die and interior walls of the cavity, and further comprising:nforming a c…d2+1

›11.↳ 1The method of claim 1, further comprisingnforming a capacitor below the upper surface of the interposer, the capacitor having a pair of electrodes ele…d2+1

›12.↳ 1An integrated circuit package made in accordance with the method of claim 1.d2

›14.independentAn integrated circuit package, comprising:na first substrate having a first region and a second region, the first region at least partially defining a…+6

›15.↳ 14The integrated circuit package of claim 14, wherein at least one of the first and second substrates comprises a semiconductor, glass, ceramic, or a po…d2

›16.↳ 14The integrated circuit package of claim 14, wherein at least one of the pair of electroconductive plates comprises a doped semiconductor, tantalum (Ta…d2

›17.↳ 14The integrated circuit package of claim 14, wherein the dielectric comprises Parylene, silicon oxide (SiO2), hafnium oxide (HfO2), tantalum pentoxide …d2

›18.↳ 14The integrated circuit package of claim 14, wherein the first region of the first substrate comprises a doped semiconductor.d2

›19.↳ 14The integrated circuit package of claim 14, wherein the metal-to-metal bond comprises an aluminum-to-aluminum (AL-to-AL) bond, a gold-to-gold (Auâ€”Au…d2

›20.↳ 14The integrated circuit package of claim 14, whereinnthe second substrate further includes a capacitor disposed below the upper surface thereof, the ca…d2

Classifications

2 codes

IPC · International Patent Classification

Section H — Electricity

H01L21/00
H01L21/56

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1.3 y

480 days filing → grant

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Bradley K Smith

art unit 2817 · TC 2800

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