Inventor
Hong Shen
Inventor
Palo Alto, CA, US
Overview
Patents· 68 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices29%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1029%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10DInorganic electric semiconductor devices11%
H05KPrinted circuits3%
G01NInvestigating or analysing materials by determining their chemical or physical properties2%
B81BMicrostructural devices or systems, e.g. micromechanical devices2%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems2%
G01JMeasurement of intensity, velocity, spectral content, polarisation, phase or pulse characteristics of infrared, visible or ultraviolet light2%
G02BOptical elements, systems or apparatus1%
PatentTitleYear
11,039,614Solid herbicide compositions containing fluroxypyr-meptyl202110,849,240Contact structures with porous networks for solder connections, and methods of fabricating same202010,629,468Device packaging using a recyclable carrier substrate202010,623,710HD color imaging using monochromatic CMOS image sensors integrated in 3D package202010,586,759Interconnection substrates for interconnection between circuit modules, and methods of manufacture202010,535,564Structures and methods for reliable packages202010,531,574Contact structures with porous networks for solder connections, and methods of fabricating same202010,522,457Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates201910,515,926System and method for providing 3D wafer assembly with known-good-dies201910,490,520Multichip modules and methods of fabrication201910,483,248Wafer level chip scale filter packaging using semiconductor wafers with through wafer vias201910,446,456Integrated circuits protected by substrates with cavities, and methods of manufacture201910,431,648Making electrical components in handle wafers of integrated circuit packages201910,340,186Method for reducing cross contamination in integrated circuit manufacturing201910,256,177Integrated interposer solutions for 2D and 3D IC packaging201910,204,977Making electrical components in handle wafers of integrated circuit packages201910,177,086Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates201910,178,363HD color imaging using monochromatic CMOS image sensors integrated in 3D package201910,163,833Multichip modules and methods of fabrication201810,014,243Interconnection substrates for interconnection between circuit modules, and methods of manufacture20189,947,618Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates20189,905,523'Microelectronic assemblies formed using metal silicide, and methods of fabrication'20189,905,507'Circuit assemblies with multiple interposer substrates, and methods of fabrication'20189,899,281'Integrated circuits protected by substrates with cavities, and methods of manufacture'20189,888,584'Contact structures with porous networks for solder connections, and methods of fabricating same'20189,865,675'Making multilayer 3D capacitors using arrays of upstanding rods or ridges'20189,859,234'Methods and structures to repair device warpage'20189,831,302Making electrical components in handle wafers of integrated circuit packages20179,825,002'Flipped die stack'20179,824,974'Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies'20179,812,406'Microelectronic assemblies with cavities, and methods of fabrication'20179,755,592'Power amplifier modules including tantalum nitride terminated through wafer via and related systems, devices, and methods'20179,754,866'Reversed build-up substrate for 2.5D'20179,741,620'Structures and methods for reliable packages'20179,741,649'Integrated interposer solutions for 2D and 3D IC packaging'20179,691,696'Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication'20179,691,702'Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates'20179,666,560'Multi-chip microelectronic assembly with built-up fine-patterned circuit structure'20179,666,508'Gallium arsenide devices with copper backside for direct die solder attach'20179,666,559'Multichip modules and methods of fabrication'20179,583,426'Multi-layer substrates suitable for interconnection between circuit modules'20179,548,273'Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies'20179,536,862'Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture'20179,530,719'Direct die solder of gallium arsenide integrated circuit dies and methods of manufacturing gallium arsenide wafers'20169,508,638'Making electrical components in handle wafers of integrated circuit packages'20169,502,347'Microelectronic assemblies formed using metal silicide, and methods of fabrication'20169,478,504'Microelectronic assemblies with cavities, and methods of fabrication'20169,437,536'Reversed build-up substrate for 2.5D'20169,412,806'Making multilayer 3D capacitors using arrays of upstanding rods or ridges'20169,402,312'Circuit assemblies with multiple interposer substrates, and methods of fabrication'20169,397,038'Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates'20169,324,626'Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication'20169,252,127'Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture'20169,231,068'Methods of stress balancing in gallium arsenide wafer processing'20169,165,793'Making electrical components in handle wafers of integrated circuit packages'20159,117,827'Making electrical components in handle wafers of integrated circuit packages'20159,093,506'Process for fabricating gallium arsenide devices with copper contact layer'20159,041,472'Power amplifier modules including related systems, devices, and methods'20159,019,541'Device and method for synchronization in digital printing'20158,998,359'Method and apparatus for controlling multicolor overprint of intermittent print device'20158,900,969'Methods of stress balancing in gallium arsenide wafer processing'20148,415,805'Etched wafers and methods of forming the same'20137,923,842'GaAs integrated circuit device and method of attaching same'20117,656,863'Method for soft switch call control and soft switch device using the same'20105,270,797'Method and apparatus for determining a material\'s characteristics by photoreflectance using improved computer control'19935,260,772'Method and apparatus for determining a material\'s characteristics by photoreflectance'19935,255,071'Photoreflectance method and apparatus utilizing acousto-optic modulation'19935,255,070'Method for determining interface properties of semiconductor materials by photoreflectance'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993Patents assigned to POLLAK FRED H (3)· patent assignee history
1993Patents assigned to SHEN HONG EN (3)· patent assignee history
1993Based in Eatontown, NJ, US· patent location history
2011–2020Patents assigned to SKYWORKS SOLUTIONS INC (12)· patent assignee history
2011–2013Based in Camarillo, CA, US· patent location history
2013–2015Patents assigned to SHEN HONG (3)· patent assignee history
2014–2019Based in Oak Park, CA, US· patent location history
2015–2020Patents assigned to INVENSAS CORP (47)· patent assignee history
2015Based in Beijing, CN· patent location history
2016–2020Based in Palo Alto, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INVENSAS CORP | 47 | 2015–2020 |
| SKYWORKS SOLUTIONS INC | 12 | 2011–2020 |
| POLLAK FRED H | 3 | 1993 |
| SHEN HONGself | 3 | 2013–2015 |
| SHEN HONG ENself | 3 | 1993 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 48 | 2016–2020 |
| Oak Park, California, US | 10 | 2014–2019 |
| Eatontown, New Jersey, US | 4 | 1993 |
| Beijing, CN | 2 | 2015 |
| Camarillo, California, US | 2 | 2011–2013 |