Inventor
Liang Wang
Inventor
Milpitas, CA, US
Overview
Patents· 93 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices30%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1027%
H10DInorganic electric semiconductor devices8%
H10HInorganic light-emitting semiconductor devices having potential barriers6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
H05KPrinted circuits4%
B81BMicrostructural devices or systems, e.g. micromechanical devices3%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems3%
F21KNon-electric light sources using luminescence1%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%
PatentTitleYear
10,879,210Bonded structures202010,879,207Bonded structures202010,849,240Contact structures with porous networks for solder connections, and methods of fabricating same202010,790,262Low temperature bonded structures202010,790,222Bonding of laminates with electrical interconnects202010,748,858High yield substrate assembly202010,658,313Selective recess202010,629,577Direct-bonded LED arrays and applications202010,623,710HD color imaging using monochromatic CMOS image sensors integrated in 3D package202010,600,761Nanoscale interconnect array for stacked dies202010,586,759Interconnection substrates for interconnection between circuit modules, and methods of manufacture202010,586,785Embedded graphite heat spreader for 3DIC202010,546,834Multi-chip modules formed using wafer-level processing of a reconstituted wafer202010,546,832Bonded structures202010,535,564Structures and methods for reliable packages202010,531,574Contact structures with porous networks for solder connections, and methods of fabricating same202010,522,457Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates201910,522,499Bonded structures201910,515,926System and method for providing 3D wafer assembly with known-good-dies201910,508,030Seal for microelectronic assembly201910,490,520Multichip modules and methods of fabrication201910,440,822Interposers with electrically conductive features having different porosities201910,431,648Making electrical components in handle wafers of integrated circuit packages201910,396,041High yield substrate assembly201910,332,854Anchoring structure of fine pitch bva201910,325,880Hybrid 3D/2.5D interposer201910,304,803Nanoscale interconnect array for stacked dies201910,283,445Bonding of laminates with electrical interconnects201910,217,720Multi-chip modules formed using wafer-level processing of a reconstitute wafer201910,204,977Making electrical components in handle wafers of integrated circuit packages201910,177,114Hybrid 3D/2.5D interposer201910,178,363HD color imaging using monochromatic CMOS image sensors integrated in 3D package201910,177,086Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates201910,163,833Multichip modules and methods of fabrication201810,014,243Interconnection substrates for interconnection between circuit modules, and methods of manufacture201810,008,652Light emitting diode device with reconstituted LED components on substrate201810,002,844Bonded structures20189,953,957Embedded graphite heat spreader for 3DIC20189,947,618Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates20189,947,643Inverted optical device20189,905,523'Microelectronic assemblies formed using metal silicide, and methods of fabrication'20189,888,584'Contact structures with porous networks for solder connections, and methods of fabricating same'20189,871,019'Flipped die stack assemblies with leadframe interconnects'20189,865,675'Making multilayer 3D capacitors using arrays of upstanding rods or ridges'20189,832,887Micro mechanical anchor for 3D architecture20179,831,302Making electrical components in handle wafers of integrated circuit packages20179,824,974'Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies'20179,825,002'Flipped die stack'20179,812,433'Batch process fabrication of package-on-package microelectronic assemblies'20179,812,406'Microelectronic assemblies with cavities, and methods of fabrication'20179,766,537'Mask'20179,769,923'Interposers'20179,754,866'Reversed build-up substrate for 2.5D'20179,741,620'Structures and methods for reliable packages'20179,691,696'Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication'20179,691,702'Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates'20179,673,124'Device and method for localized underfill'20179,666,560'Multi-chip microelectronic assembly with built-up fine-patterned circuit structure'20179,666,559'Multichip modules and methods of fabrication'20179,620,436'Light emitting diode device with reconstituted LED components on substrate'20179,583,426'Multi-layer substrates suitable for interconnection between circuit modules'20179,583,671'Quantum efficiency of multiple quantum wells'20179,570,385'Method for fabrication of interconnection circuitry with electrically conductive features passing through a support and comprising core portions formed using nanoparticle-containing inks'20179,548,273'Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies'20179,508,638'Making electrical components in handle wafers of integrated circuit packages'20169,502,347'Microelectronic assemblies formed using metal silicide, and methods of fabrication'20169,496,154'Use of underfill tape in microelectronic components, and microelectronic components with cavities coupled to through-substrate vias'20169,478,504'Microelectronic assemblies with cavities, and methods of fabrication'20169,461,196'Non-crystalline inorganic light emitting diode'20169,437,536'Reversed build-up substrate for 2.5D'20169,412,806'Making multilayer 3D capacitors using arrays of upstanding rods or ridges'20169,397,038'Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates'20169,390,998'Heat spreading substrate'20169,356,006'Batch process fabrication of package-on-package microelectronic assemblies'20169,348,170'Color filter substrate and display device'20169,349,614'Device and method for localized underfill'20169,324,626'Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication'20169,293,641'Inverted optical device'20169,214,454'Batch process fabrication of package-on-package microelectronic assemblies'20159,165,793'Making electrical components in handle wafers of integrated circuit packages'20159,117,827'Making electrical components in handle wafers of integrated circuit packages'20159,070,849'Parallel plate slot emission array'20158,975,616'Quantum efficiency of multiple quantum wells'20158,941,111'Non-crystalline inorganic light emitting diode'20158,912,024'Front facing piggyback wafer assembly'20148,900,974'High yield substrate assembly'20148,841,204'High yield substrate assembly'20148,816,383'High performance light emitting diode with vias'20148,664,681'Parallel plate slot emission array'20148,638,334'Selectively displaying surfaces of an object model'20147,703,925'Miniature projector module having effective utilization of light with two polarizations'20107,385,285'Light assembly'20084,709,731'Flexible element of (dual) wave crest'1987Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1987–2016Patents assigned to WANG LIANG (9)· patent assignee history
2008–2010Based in Taipei, TW· patent location history
2014–2020Patents assigned to INVENSAS CORP (77)· patent assignee history
2014–2016Patents assigned to MOHAMMED ILYAS (7)· patent assignee history
2014–2016Patents assigned to BEROZ MASUD (5)· patent assignee history
2014–2020Based in Milpitas, CA, US· patent location history
2016–2017Based in Beijing, CN· patent location history
2017Based in San Jose, CA, US· patent location history
2018–2020Patents assigned to INVENSAS BONDING TECH INC (8)· patent assignee history
2019–2020Based in Newark, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INVENSAS CORP | 77 | 2014–2020 |
| WANG LIANGself | 9 | 1987–2016 |
| INVENSAS BONDING TECH INC | 8 | 2018–2020 |
| MOHAMMED ILYAS | 7 | 2014–2016 |
| BEROZ MASUD | 5 | 2014–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Milpitas, California, US | 73 | 2014–2020 |
| Newark, California, US | 12 | 2019–2020 |
| Beijing, CN | 2 | 2016–2017 |
| Taipei, TW | 2 | 2008–2010 |
| San Jose, California, US | 1 | 2017 |