A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.

Claims

25 · 3 independent · depth 4

25 granted claims

›1.independentA semiconductor device comprising:na first semiconductor chip;a routing plane comprising a plurality of substantially parallel spaced apart conductive…+8

›2.↳ 1The device of claim 1, wherein the first semiconductor chip and the routing plane are encapsulated by an encapsulating material.d2

›3.↳ 1The device of claim 1, wherein the first connecting line is electrically coupled to the one of the plurality of substantially parallel spaced apart co…d2+1

›5.↳ 1The device of claim 1, wherein the routing plane includes at least one of a silicon substrate, a polymer substrate, a ceramic substrate, or a metal su…d2

›6.↳ 1The device of claim 1, wherein the one of the plurality of substantially parallel spaced apart conductive routing lines is coplanar with an active sid…d2

›7.↳ 1The device of claim 1, wherein the first connecting line is formed in a redistribution layer.d2

›8.↳ 1The device of claim 1, further comprising:na crossing line that crosses the routing plane and is electrically coupled to the first semiconductor chip …d2+1

›10.independentA semiconductor device comprising:nat least one semiconductor chip embedded in a molding and having at least one contact element;at least one routing …+8

›11.↳ 10The device of claim 10, wherein the at least one routing plane is disposed between the first semiconductor chip and the second semiconductor chip.d2

›12.↳ 10The device of claim 10, further comprising:na plurality of via openings formed in the first insulating layer and structured over the at least one cont…d2+2

›15.↳ 10The device of claim 10, further comprising:na second insulating layer disposed over the redistribution layer.d2+3

›19.independentA method for routing electrical connections comprising:nproviding a first semiconductor chip and a routing plane including a plurality of substantiall…+6

›20.↳ 19The method of claim 19, wherein providing the first semiconductor chip and the routing plane comprises:nproviding at least one contact element in the …d2

›21.↳ 19The method of claim 19, wherein forming a plurality of via openings in the first insulating layer comprises:nforming a plurality of via openings over …d2

›22.↳ 19The method of claim 19, further comprising:nencapsulating the first semiconductor chip and the routing plane with an encapsulating material.d2

›23.↳ 19The method of claim 19, further comprising:napplying a solder stop layer over the first redistribution layer; andstructuring the solder stop layer to …d2

›24.↳ 19The method of claim 19, further comprising:napplying a second insulating layer over the first redistribution layer; andapplying a second redistributio…d2+1

Classifications

16 codes

IPC · International Patent Classification

Section H — Electricity

H01L23/48
H01L21/768

USPC · US Patent Classification

257/773257/724257/E23.01257/686257/723257/685257/698257/728257/E21.575257/696257/777257/691257/778257/692

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Pendency

2.6 y

952 days filing → grant

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non-final + final

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1 RCE

Examiner

A O Williams

art unit 2826 · TC 2800

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Citations: 13 back · 0 forward

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1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20120049375 A1	1 Mar 2012

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