Inventor
Andreas Wolter
Inventor
Regensburg, DE
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1032%
H01LSemiconductor devices26%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H01FMagnets6%
G06FElectric digital data processing4%
H01QAntennas, i.e. radio aerials3%
H04BTransmission3%
H10DInorganic electric semiconductor devices3%
G01RMeasuring electric variables2%
G02BOptical elements, systems or apparatus2%
PatentTitleYear
11,127,813Semiconductor inductors202111,107,763Interconnect structure for stacked die in a microelectronic device202111,018,114Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory202110,896,780Resonant LC tank package and method of manufacture202110,867,934Component magnetic shielding for microelectronic devices202010,816,742Integrated circuit packages including an optical redistribution layer202010,784,033Vertical inductor for WLCSP202010,727,197Embedded-bridge substrate connectors and methods of assembling same202010,535,578Semiconductor devices, and a method for forming a semiconductor device202010,522,454Microelectronic package having a passive microelectronic device disposed within a package body201910,522,485Electrical device and a method for forming an electrical device201910,490,527Vertical wire connections for integrated circuit package201910,431,545Cross-connected multi-chip modules coupled by silicon bent-bridge interconnects and methods of assembling same201910,411,000Microelectronic package with illuminated backside exterior201910,403,609System-in-package devices and methods for forming system-in-package devices201910,403,602Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory201910,373,844Integrated circuit package configurations to reduce stiffness201910,366,968Interconnect structure for a microelectronic device201910,319,688Antenna on ceramics for a packaged die201910,290,412Vertical inductor for WLCSP201910,228,725Flexible band wearable electronic device201910,229,858Conductive paths through dielectric with a high aspect ratio for semiconductor devices201910,209,466Integrated circuit packages including an optical redistribution layer201910,141,265Bent-bridge semiconductive apparatus201810,121,726Cooler for semiconductor devices20189,997,444Microelectronic package having a passive microelectronic device disposed within a package body20189,985,005Chip package-in-package20189,921,694'Wearable computing device'20189,865,387'Electronic package with coil formed on core'20189,819,327'Bulk acoustic wave resonator tuner circuits'20179,711,492'Three dimensional structures within mold compound'20179,653,324'Integrated circuit package configurations to reduce stiffness'20179,653,439'Three dimensional structures within mold compound'20179,576,918'Conductive paths through dielectric with a high aspect ratio for semiconductor devices'20179,397,019'Integrated circuit package configurations to reduce stiffness'20169,312,198'Chip package-in-package and method thereof'20168,786,105'Semiconductor device with chip having low-k-layers'20148,779,564'Semiconductor device with capacitive coupling structure'20148,598,709'Method and system for routing electrical connections of semiconductor chips'20138,415,803'Method and system for routing electrical connections of semiconductor chips'20138,093,711'Semiconductor device'20128,049,310'Semiconductor device with an interconnect element and method for manufacture'20117,928,590'Integrated circuit package with a heat dissipation device'20117,274,107'Semiconductor device'20077,274,102'Contacting device, testing method and corresponding production method'20077,080,988'Flexible contact-connection device'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2013Patents assigned to INFINEON TECHNOLOGIES AG (5)· patent assignee history
2006–2007Based in Pliening, DE· patent location history
2007–2011Based in Markt Schwaben, DE· patent location history
2011–2021Based in Regensburg, DE· patent location history
2012–2017Patents assigned to MEYER THORSTEN (4)· patent assignee history
2012–2017Patents assigned to WOLTER ANDREAS (4)· patent assignee history
2014–2021Patents assigned to INTEL IP CORP (27)· patent assignee history
2017–2021Patents assigned to INTEL CORP (8)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL IP CORP | 27 | 2014–2021 |
| INTEL CORP | 8 | 2017–2021 |
| INFINEON TECHNOLOGIES AG | 5 | 2006–2013 |
| MEYER THORSTEN | 4 | 2012–2017 |
| WOLTER ANDREASself | 4 | 2012–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Regensburg, DE | 42 | 2011–2021 |
| Markt Schwaben, DE | 2 | 2007–2011 |
| Pliening, DE | 2 | 2006–2007 |