US Patent 8,230,199 — Perform frame management function instruction for setting storage keys and clearing blocks of main storage

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Abstract

What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block.

Claims

21 · 3 independent · depth 3

21 granted claims

›1.independentA computer program product for executing a perform frame management function (PFMF) machine instruction in a processor of a computer system of a machi…+7

A computer program product for executing a perform frame management function (PFMF) machine instruction in a processor of a computer system of a machine architecture, the computer system configured to translate a virtual address into a translated address of a block of main storage in the computer system having a hierarchy of translation tables used for translation of said virtual address to obtain any one of an absolute address of a large block of main storage or a real address of a small block of main storage, wherein a real address is subject to prefixing to form an absolute address, wherein each block of main storage has an associated storage key separate and distinct from any of said translation tables, said PFMF machine instruction defined for said machine architecture, the computer program product comprising:na storage medium readable by said computer system, said computer readable medium storing instructions for performing a method comprising:fetching for execution said PFMF machine instruction, the PFMF machine instruction comprising an opcode field, a first register field for identifying a first general register and a second register field for identifying a second general register; andexecuting the PFMF machine instruction, the executing comprising:nobtaining frame management information from said first general register wherein said frame management information comprises a set key control (SK) bit, a key field for specifying a plurality of access-protection bits, a clear frame control (CF) bit, and an indicator field (FSC) specifying the size of a frame of main storage, the frame of main storage being one of a large block of main storage and a small block of main storage, the access-protection bits comprising access-control bits (ACC);obtaining an operand address of a frame of main storage from said second general register;in response to the setting of said set key control bit being 1, setting storage access protection bits of a storage key associated with the frame of main storage to a value of said access-protection bits, the storage access protection bits comprising storage ACC bits for matching with a program access key to determine accessibility of a main storage location; andin response to the setting of said clear frame control bit being 1, clearing main storage of the frame of main storage by setting all bytes of the frame of main storage to zero.

›2.↳ 1The computer program product according to claim 1, wherein said operand address is one of an absolute address of a large block of main storage and a r…d2

›3.↳ 1The computer program product according to claim 1, wherein said key field associated with a frame of main storage further comprises a storage fetch-pr…d2+1

›5.↳ 1The computer program product according to claim 1, wherein the PFMF machine instruction is not native to the PFMF machine instruction architecture of …d2

›6.↳ 1The computer program product according to claim 1, further comprising:nin response to said set key control bit being 0, not setting storage access pro…d2

›7.↳ 1The computer program product according to claim 1, further comprising:nresponsive to determining that said FSC specifies the size of the frame is a la…d2+1

›8.independentA system for executing a perform frame management function (PFMF) machine instruction in a processor of a computer system of a machine architecture, t…+5

A system for executing a perform frame management function (PFMF) machine instruction in a processor of a computer system of a machine architecture, the computer system configured to translate a virtual address into a translated address of a lock of main storage in the computer system, the PFMF machine instruction defined for said machine architecture, the system comprising:na main storage configured to store machine instructions and a hierarchy of translation tables used for dynamic address translation of said virtual address into a real address or absolute address of a desired block of data in said main storage to obtain any one of an absolute address of a large block of main storage or a real address of a small block of main storage, wherein a real address is subject to prefixing, said real address being subject to a prefixing operation to form an absolute address, wherein each block of main storage has an associated storage key separate and distinct from any of said translation tables; anda processor in communication with said computer memory, said processor configured to interpret said machine instruction and access said hierarchy of translation tables stored in said main storage, said processor performing a method comprising:fetching for execution said PFMF machine instruction, the PFMF machine instruction comprising an opcode field, a first register field for identifying a first general register and a second register field for identifying a second general register; andexecuting the PFMF machine instruction which has bccn fetched, the executing comprising:nobtaining frame management information from said first general register wherein said frame management information comprises a set key control (SK) bit, a key field for specifying a plurality of access-protection bits, a clear frame control (CF) bit, and an indicator field (FSC) specifying the size of a frame of main storage, the frame of main storage being one of a large block of main storage and a small block of main storage, the access-protection bits comprising access-control bits (ACC);obtaining an operand address of a frame of main storage from said second general register;in response to said set key control bit being 1, setting storage access protection bits of a storage key associated with the frame of main storage to a value of said access-protection bits, the storage access protection bits comprising storage ACC bits for matching with a program access key to determine accessibility of a main storage location; andin response to the setting of said clear frame control bit being 1, clearing main storage of the frame of main storage by setting all bytes of the main storage to zero.

›9.↳ 8The system according to claim 8, wherein said operand address is one of an absolute address of a large block of main storage and a real address of a s…d2

›10.↳ 8The system according to claim 8, wherein said key field associated with a frame of main storage further comprises a storage fetch-protection bit, a st…d2+1

›13.↳ 8The system according to claim 8, further comprising:nin response to said set key control bit being 0, not setting storage access protection bits of th…d2

›14.↳ 8The system according to claim 8, further comprising:nresponsive to determining that said FSC specifies the size of the frame is a large frame of a lar…d2

›15.independentA computer implemented method for executing a perform frame management function (PFMF) machine instruction in a processor of a computer system of a ma…+6

A computer implemented method for executing a perform frame management function (PFMF) machine instruction in a processor of a computer system of a machine architecture, the computer system configured to translate a virtual address into a translated address of a block of data in main storage in the computer system having a hierarchy of translation tables used for translation of said virtual address to obtain any one of an absolute address of a large block of main storage or a real address of a small block of main storage, wherein a real address is subject to prefixing to form an absolute address, wherein each block of main storage has an associated storage key separate and distinct from any of said translation tables, said PFMF machine instruction defined for said machine architecture, the method comprising:nfetching for execution said PFMF machine instruction, the PFMF machine instruction comprising an opcode field, a first register field for identifying a first general register and a second register field for identifying a second general register; andexecuting the PFMF machine instruction which has been fetched, the executing comprising:nobtaining frame management information from said first general register wherein said frame management information comprises a set key control (SK) bit, a key field for specifying a plurality of access-protection bits, a clear frame control (CF) bit, and an indicator field (FSC) specifying the size of a frame of main storage, the frame of main storage being one of a large block of main storage and a small block of main storage, the access-protection bits comprising access-control bits (ACC);obtaining an operand address of a frame of main storage from said second general register;in response to of said set key control bit being 1, setting storage access protection bits of a storage key associated with the frame of main storage to a value of said access-protection bits, the storage access protection bits comprising storage ACC bits for matching with a program access key to determine accessibility of a main storage location; andin response to the setting of said clear frame control bit being 1, clearing main storage of the frame of main storage by setting all bytes of the main storage to zero.

›16.↳ 15The method according to claim 15, wherein said operand address is one of an absolute address of a large block of main storage and a real address of a …d2

›17.↳ 15The method according to claim 15, wherein said key field associated with a frame of main storage further comprises a storage fetch-protection bit, a s…d2+1

›19.↳ 15The method according to claim 15, wherein the PFMF machine instruction is not native to the PFMF machine instruction architecture of the processor, fu…d2

›20.↳ 15The method according to claim 15, further comprising:nin response to said set key control bit being 0, not setting storage access protection bits of t…d2

›21.↳ 15The method according to claim 15, further comprising:nresponsive to determining that said FSC specifies the size of the frame is a large frame of a la…d2

Classifications

4 codes

IPC · International Patent Classification

Section G — Physics

G06F12/08

USPC · US Patent Classification

711/203711/206711/156

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Midys Rojas

art unit 2185 · TC 2100

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›Priority documents — 1

Type	Document	Date
related publication	US 20090187724 A1	23 Jul 2009

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