Inventor

Damian L. Osisek

Inventor
Vestal, NY, US

Overview

156→
Patents
1989–2021
Patent span
Physics
Primary field (CPC G)

Patents· 156 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing60%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
G01SRadio direction-finding3%
G11BInformation storage based on relative movement between record carrier and transducer3%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%
H04BTransmission3%
H04JMultiplex communication3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H04MTelephonic communication3%
H04NPictorial communication, e.g. television3%
PatentTitleYear
11,086,624Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor202111,074,180Creating a dynamic address translation with translation exception qualifiers202110,977,190Dynamic address translation with access control in an emulator environment202110,908,903Efficiency for coordinated start interpretive execution exit for a multithreaded processor202110,802,986Marking to indicate memory used to back address translation structures202010,776,112Performing an operation absent host intervention202010,768,832Managing storage protection faults202010,698,845Set buffer state instruction202010,684,800Facilitating processing within computing environments supporting pageable guests202010,664,269Function virtualization facility for function query of a processor202010,657,085Interruption facility for adjunct processor queues202010,620,877Managing a collection of data202010,613,895Virtualization of storage buffers used by asynchronous processes202010,521,231Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor201910,496,292Saving/restoring guarded storage controls in a virtualized environment201910,445,248Host page management using active guest page table indicators201910,423,539Dynamic address translation with access control in an emulator environment201910,409,745Interruption facility for adjunct processor queues201910,394,488Managing a collection of data201910,360,032Performing an operation absent host intervention201910,268,499Virtualization of storage buffers used by asynchronous processes201910,241,910Creating a dynamic address translation with translation exception qualifiers201910,223,283Selective purging of PCI I/O address translation buffer201910,223,300Set buffer state instruction201910,223,015Managing storage protection faults201910,176,111Host page management using active guest page table indicators201910,133,515Facilitating processing within computing environments supporting pageable guests201810,089,111Performing an operation absent host intervention201810,078,585Creating a dynamic address translation with translation exception qualifiers201810,019,393Interruption facility for adjunct processor queues20189,971,533Managing storage protection faults20189,934,159Dynamic address translation with fetch protection in an emulated environment20189,921,848'Address expansion and contraction in a multithreading computer system'20189,921,849'Address expansion and contraction in a multithreading computer system'20189,898,290'Efficiency for coordinated start interpretive execution exit for a multithreaded processor'20189,898,289'Coordinated start interpretive execution exit for a multithreaded processor'20189,886,392'Selective purging of PCI I/O address translation buffer'20189,886,391'Selective purging of PCI I/O address translation buffer'20189,880,942'Selective purging of PCI I/O address translation buffer'20189,880,785'Managing a collection of data'20189,851,969Function virtualization facility for function query of a processor20179,804,846'Thread context preservation in a multithreading computer system'20179,804,847'Thread context preservation in a multithreading computer system'20179,778,869'Managing storage protection faults'20179,772,867'Control area for managing multiple threads in a computer'20179,760,511'Efficient interruption routing for a multithreaded processor'20179,652,383'Managing a collection of data'20179,606,799'Performing a clear operation absent host intervention'20179,594,661'Method for executing a query instruction for idle time accumulation among cores in a multithreading computer system'20179,594,660'Multithreading computer system and program product for executing a query instruction for idle time accumulation among cores'20179,542,260'Managing storage protection faults'20179,459,875'Dynamic enablement of multithreading'20169,459,873'Run-time instrumentation monitoring of processor characteristics'20169,454,372'Thread context restoration in a multithreading computer system'20169,454,462'Run-time instrumentation monitoring for processor characteristic changes'20169,417,876'Thread context restoration in a multithreading computer system'20169,389,862'Thread context restoration in a multithreading computer system'20169,378,128'Dynamic address translation with fetch protection in an emulated environment'20169,354,883'Dynamic enablement of multithreading'20169,354,873'Performing a clear operation absent host intervention'20169,342,352'Guest access to address spaces of adapter'20169,323,560'Interpreting I/O operation requests from pageable guests without host intervention'20169,317,460'Program event recording within a transactional environment'20169,311,259'Program event recording within a transactional environment'20169,251,106'Interruption facility for adjunct processor queues'20169,251,085'Performing a clear operation absent host intervention'20169,244,856'Dynamic address translation with translation table entry format control for identifying format of the translation table entry'20169,235,539'Program event recording within a transactional environment'20169,223,574'Start virtual execution instruction for dispatching multiple threads in a computer'20159,218,185'Multithreading capability information retrieval'20159,183,027'Facilitating processing within computing environments supporting pageable guests'20159,158,543'Query sampling information instruction'20159,158,711'Creating a program product or system for executing a perform frame management instruction'20159,122,634'Use of test protection instruction in computing environments that support pageable guests'20159,122,477'Execution of a perform frame management function instruction'20159,092,351'Creating a dynamic address translation with translation exception qualifier'20159,086,905'Interpreting I/O operation requests from pageable guests without host intervention'20159,021,225'Dynamic address translation with fetch protection in an emulated environment'20159,003,134'Emulation of a dynamic address translation with change record override on a machine of another architecture'20158,972,670'Use of test protection instruction in computing environments that support pageable guests'20158,949,831'Dynamic virtual machine domain configuration and virtual machine relocation management'20158,935,504'Execution of a perform frame management function instruction'20158,930,603'Interruption facility for adjunct processor queues'20158,930,673'Load page table entry address instruction execution based on an address translation format control field'20158,909,899'Emulating execution of a perform frame management instruction'20148,904,390'Interpreting I/O operation requests from pageable guests without host intervention'20148,862,834'Shared memory translation facility'20148,819,393'Facilitating management of storage of a pageable mode virtual environment absent intervention of a host of the environment'20148,806,178'Set sampling controls instruction'20148,752,053'Facilitating processing within computing environments supporting pageable guests'20148,707,000'Execution of a perform frame management function instruction'20148,701,120'Virtualization of storage buffers used by asynchronous processes'20148,683,176'Dynamic address translation with translation exception qualifier'20148,677,098'Dynamic address translation with fetch protection'20148,677,077'Use of test protection instruction in computing environments that support pageable guests'20148,639,911'Load page table entry address instruction execution based on an address translation format control field'20148,631,216'Dynamic address translation with change record override'20148,621,180'Dynamic address translation with translation table entry format control for identifying format of the translation table entry'20138,533,714'Dynamic virtual machine domain configuration and virtual machine relocation management'20138,527,715'Providing a shared memory translation facility'20138,516,227'Set program parameter instruction'20138,504,754'Identification of types of sources of adapter interruptions'20138,495,326'Execution of a perform frame management function instruction'20138,495,633'Interpreting I/O operation requests from pageable guests without host intervention'20138,489,853'Executing a perform frame management instruction'20138,478,966'Query sampling information instruction'20138,478,922'Controlling a rate at which adapter interruption requests are processed'20138,468,284'Converting a message signaled interruption into an I/O adapter event notification to a guest operating system'20138,458,438'System, method and computer program product for providing quiesce filtering for shared memory'20138,458,387'Converting a message signaled interruption into an I/O adapter event notification to a guest operating system'20138,417,916'Perform frame management function instruction for setting storage keys and clearing blocks of main storage'20138,417,837'Set sampling controls instruction'20138,387,062'Virtualization of storage buffers used by asynchronous processes'20138,387,049'Facilitating processing within computing environments supporting pageable guests'20138,380,907'Method, system and computer program product for providing filtering of GUEST2 quiesce requests'20138,364,912'Use of test protection instruction in computing environments that support pageable guests'20138,335,906'Perform frame management function instruction for clearing blocks of main storage'20128,316,172'Interruption facility for adjunct processor queues'20128,239,649'Clearing guest frames absent paging-in to host main storage'20128,230,199'Perform frame management function instruction for setting storage keys and clearing blocks of main storage'20128,214,622'Facilitating management of storage of a pageable mode virtual environment absent intervention of a host of the environment'20128,196,139'Interpreting I/O operation requests from pageable guests without host intervention'20128,176,279'Managing use of storage by multiple pageable guests of a computing environment'20128,176,280'Use of test protection instruction in computing environments that support pageable guests'20128,151,083'Dynamic address translation with frame management'20128,117,417'Dynamic address translation with change record override'20128,103,851'Dynamic address translation with translation table entry format control for indentifying format of the translation table entry'20128,095,773'Dynamic address translation with translation exception qualifier'20128,086,811'Optimizations of a perform frame management function issued by pageable guests'20118,082,405'Dynamic address translation with fetch protection'20118,041,923'Load page table entry address instruction execution based on an address translation format control field'20118,041,922'Enhanced dynamic address translation with load real address function'20118,037,278'Dynamic address translation with format control'20118,019,964'Dynamic address translation with DAT protection'20118,019,922'Interruption facility for adjunct processor queues'20117,996,835'System, method and program for managing communication with multiple configurations for virtual machine'20117,954,099'Demultiplexing grouped events into virtual event queues while in two levels of virtualization'20117,941,799'Interpreting I/O operation requests from pageable guests without host intervention'20117,827,321'Central processing unit measurement facility'20107,725,894'Enhanced un-privileged computer instruction to store a facility list'20107,650,469'Determining whether a non-running processor has access to an address space'20107,552,436'Memory mapped input/output virtualization'20097,543,095'Managing input/output interruptions in non-dedicated interruption hardware environments'20097,523,291'System and method for testing for memory address aliasing errors'20097,500,037'System, method and program for managing locks'20097,464,249'System and method for alias mapping of address space'20087,454,548'Managing input/output interruptions in non-dedicated interruption hardware environments, and methods therefor'20087,380,041'Managing input/output interruptions in non-dedicated interruption hardware environments'20087,254,733'Method of shutting down virtual machines in an orderly manner'20077,197,585'Method and apparatus for managing the execution of a broadcast instruction on a guest processor'20077,130,949'Managing input/output interruptions in non-dedicated interruption hardware environments'20066,941,549'Communicating between programs having different machine context organizations'20055,555,385'Allocation of address spaces within virtual machine compute system'19965,410,700'Computer system which supports asynchronous commitment of data'19955,230,069'Apparatus and method for providing private and shared access to host address and data spaces by guest programs in a virtual machine computer system'19934,809,168'Passive serialization in a multitasking environment'1989

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1989–2021Patents assigned to IBM (152)· patent assignee history
1989Based in Woodstock, NY, US· patent location history
1993–2021Based in Vestal, NY, US· patent location history
2011–2016Patents assigned to OSISEK DAMIAN L (42)· patent assignee history
2011–2019Patents assigned to GREINER DAN F (24)· patent assignee history
2011–2019Patents assigned to HELLER LISA C (24)· patent assignee history
2011–2019Patents assigned to SLEGEL TIMOTHY J (15)· patent assignee history
2014–2021Based in Endicott, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM1521989–2021
OSISEK DAMIAN Lself422011–2016
GREINER DAN F242011–2019
HELLER LISA C242011–2019
SLEGEL TIMOTHY J152011–2019
Locations
LocationPatentsSpan
Vestal, New York, US1501993–2021
Endicott, New York, US52014–2021
Woodstock, New York, US11989