Inventor

Charles W. Gainey, Jr.

Inventor
Poughkeepsie, NY, US

Overview

166→
Patents
1994–2021
Patent span
Physics
Primary field (CPC G)

Patents· 166 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing93%
H04LTransmission of digital information, e.g. telegraphic communication7%
PatentTitleYear
11,029,974Architectural mode configuration202111,023,256Architectural mode configuration202110,977,190Dynamic address translation with access control in an emulator environment202110,908,903Efficiency for coordinated start interpretive execution exit for a multithreaded processor202110,831,476Compare and delay instructions202010,776,112Performing an operation absent host intervention202010,747,583Managing processing associated with selected architectural facilities202010,747,582Managing processing associated with selected architectural facilities202010,725,780Convert to zoned format from decimal floating point format202010,719,324Convert to zoned format from decimal floating point format202010,657,085Interruption facility for adjunct processor queues202010,621,007Execution of an instruction for performing a configuration virtual topology change202010,552,175Architectural mode configuration202010,545,772Architectural mode configuration202010,423,539Dynamic address translation with access control in an emulator environment201910,409,745Interruption facility for adjunct processor queues201910,387,040Configure storage class memory command201910,372,505Execution of an instruction for performing a configuration virtual topology change201910,360,032Performing an operation absent host intervention201910,303,478Convert from zoned format to decimal floating point format201910,296,344Convert from zoned format to decimal floating point format201910,169,038Compare and delay instructions201910,120,681Compare and delay instructions201810,089,111Performing an operation absent host intervention201810,061,623Execution of an instruction for performing a configuration virtual topology change201810,055,261Execution of an instruction for performing a configuration virtual topology change201810,019,393Interruption facility for adjunct processor queues20189,934,159Dynamic address translation with fetch protection in an emulated environment20189,921,848'Address expansion and contraction in a multithreading computer system'20189,921,849'Address expansion and contraction in a multithreading computer system'20189,916,185'Managing processing associated with selected architectural facilities'20189,916,186'Managing processing associated with selected architectural facilities'20189,898,290'Efficiency for coordinated start interpretive execution exit for a multithreaded processor'20189,898,289'Coordinated start interpretive execution exit for a multithreaded processor'20189,804,846'Thread context preservation in a multithreading computer system'20179,804,847'Thread context preservation in a multithreading computer system'20179,792,157'Execution of an instruction for performing a configuration virtual topology change'20179,772,867'Control area for managing multiple threads in a computer'20179,760,511'Efficient interruption routing for a multithreaded processor'20179,747,033'Configure storage class memory command'20179,606,799'Performing a clear operation absent host intervention'20179,594,576'Architectural mode configuration'20179,594,661'Method for executing a query instruction for idle time accumulation among cores in a multithreading computer system'20179,594,660'Multithreading computer system and program product for executing a query instruction for idle time accumulation among cores'20179,582,295'Architectural mode configuration'20179,542,204'Architectural mode configuration'20179,489,285'Modifying run-time-instrumentation controls from a lesser-privileged state'20169,471,315'Run-time instrumentation reporting'20169,465,716'Run-time instrumentation directed sampling'20169,459,875'Dynamic enablement of multithreading'20169,459,873'Run-time instrumentation monitoring of processor characteristics'20169,454,462'Run-time instrumentation monitoring for processor characteristic changes'20169,454,372'Thread context restoration in a multithreading computer system'20169,442,728'Run-time instrumentation indirect sampling by instruction operation code'20169,442,824'Transformation of a program-event-recording event into a run-time instrumentation event'20169,430,238'Run-time-instrumentation controls emit instruction'20169,417,876'Thread context restoration in a multithreading computer system'20169,411,591'Run-time instrumentation sampling in transactional-execution mode'20169,405,543'Run-time instrumentation indirect sampling by address'20169,405,541'Run-time instrumentation indirect sampling by address'20169,400,736'Transformation of a program-event-recording event into a run-time instrumentation event'20169,395,989'Run-time-instrumentation controls emit instruction'20169,389,862'Thread context restoration in a multithreading computer system'20169,378,128'Dynamic address translation with fetch protection in an emulated environment'20169,372,693'Run-time instrumentation sampling in transactional-execution mode'20169,372,640'Configure storage class memory command'20169,367,316'Run-time instrumentation indirect sampling by instruction operation code'20169,367,313'Run-time instrumentation directed sampling'20169,354,883'Dynamic enablement of multithreading'20169,354,873'Performing a clear operation absent host intervention'20169,335,995'Convert to zoned format from decimal floating point format'20169,335,993'Convert from zoned format to decimal floating point format'20169,335,994'Convert from zoned format to decimal floating point format'20169,329,861'Convert to zoned format from decimal floating point format'20169,330,042'Determining extended capability of a channel path'20169,323,668'Deconfigure storage class memory command'20169,286,192'Modifying run-time-instrumentation controls from a lesser-privileged state'20169,280,447'Modifying run-time-instrumentation controls from a lesser-privileged state'20169,280,346'Run-time instrumentation reporting'20169,280,448'Controlling operation of a run-time instrumentation facility from a lesser-privileged state'20169,262,236'Warning track interruption facility'20169,251,106'Interruption facility for adjunct processor queues'20169,250,903'Determining the status of run-time-instrumentation controls'20169,250,902'Determining the status of run-time-instrumentation controls'20169,251,085'Performing a clear operation absent host intervention'20169,223,574'Start virtual execution instruction for dispatching multiple threads in a computer'20159,218,185'Multithreading capability information retrieval'20159,213,661'Enable/disable adapters of a computing environment'20159,195,461'Run-time instrumentation reporting'20159,158,660'Controlling operation of a run-time instrumentation facility'20159,158,711'Creating a program product or system for executing a perform frame management instruction'20159,137,120'Emulating execution of an instruction for discovering virtual topology of a logical partitioned computer system'20159,122,477'Execution of a perform frame management function instruction'20159,116,634'Configure storage class memory command'20159,116,635'Configure storage class memory command'20159,110,741'Warning track interruption facility'20159,110,878'Use of a warning track interruption facility by a program'20159,104,509'Providing by one program to another program access to a warning track facility'20159,104,508'Providing by one program to another program access to a warning track facility'20159,098,358'Use of a warning track interruption facility by a program'20159,098,478'Warning track interruption facility'20159,037,785'Store storage class memory information command'20159,021,225'Dynamic address translation with fetch protection in an emulated environment'20159,021,179'Store storage class memory information command'20158,977,793'Determining extended capability of a channel path'20158,935,504'Execution of a perform frame management function instruction'20158,930,603'Interruption facility for adjunct processor queues'20158,909,899'Emulating execution of a perform frame management instruction'20148,850,450'Warning track interruption facility'20148,838,860'Determining extended capability of a channel path'20148,832,689'Emulating execution of an instruction for discovering virtual topology of a logical partitioned computer system'20148,819,320'Executing an instruction for performing a configuration virtual topology change'20148,707,000'Execution of a perform frame management function instruction'20148,689,230'Determination of running status of logical processor'20148,677,098'Dynamic address translation with fetch protection'20148,621,112'Discovery by operating system of information relating to adapter functions accessible to the operating system'20138,510,599'Managing processing associated with hardware events'20138,505,032'Operating system notification of actions to be taken responsive to adapter events'20138,495,326'Execution of a perform frame management function instruction'20138,489,853'Executing a perform frame management instruction'20138,478,915'Determining extended capability of a channel path'20138,417,916'Perform frame management function instruction for setting storage keys and clearing blocks of main storage'20138,335,906'Perform frame management function instruction for clearing blocks of main storage'20128,316,172'Interruption facility for adjunct processor queues'20128,301,815'Executing an instruction for performing a configuration virtual topology change'20128,276,151'Determination of running status of logical processor'20128,239,649'Clearing guest frames absent paging-in to host main storage'20128,230,199'Perform frame management function instruction for setting storage keys and clearing blocks of main storage'20128,176,279'Managing use of storage by multiple pageable guests of a computing environment'20128,151,083'Dynamic address translation with frame management'20128,095,847'Exception condition handling at a channel subsystem in an I/O processing system'20128,086,811'Optimizations of a perform frame management function issued by pageable guests'20118,082,405'Dynamic address translation with fetch protection'20118,019,964'Dynamic address translation with DAT protection'20118,019,922'Interruption facility for adjunct processor queues'20118,015,335'Performing a configuration virtual topology change and instruction therefore'20117,996,687'Product for providing a scalable trusted platform module in a hypervisor environment'20117,984,275'Computer configuration virtual topology discovery and instruction therefore'20117,961,729'Broadcast and multicast packet management'20117,954,099'Demultiplexing grouped events into virtual event queues while in two levels of virtualization'20117,940,785'Ethernet adapter packet management'20117,917,813'Exception condition determination at a control unit in an I/O processing system'20117,739,434'Performing a configuration virtual topology change and instruction therefore'20107,734,900'Computer configuration virtual topology discovery and instruction therefore'20107,725,894'Enhanced un-privileged computer instruction to store a facility list'20107,650,469'Determining whether a non-running processor has access to an address space'20107,606,965'Information handling system with virtualized I/O adapter ports'20097,587,531'Multiple logical input/output subsystem facility'20097,552,436'Memory mapped input/output virtualization'20097,493,526'System and method for supporting debugging of host channel adapters in a logical partitioning'20097,478,246'Method for providing a scalable trusted platform module in a hypervisor environment'20097,290,070'Multiple logical input/output subsystem facility'20077,277,968'Managing sets of input/output communications subadapters of an input/output subsystem'20077,234,037'Memory mapped Input/Output operations'20077,200,704'Virtualization of an I/O adapter port using enablement and activation functions'20077,197,585'Method and apparatus for managing the execution of a broadcast instruction on a guest processor'20077,177,961'Managing access, by operating system images of a computing environment, of input/output resources of the computing environment'20077,174,550'Sharing communications adapters across a plurality of input/output subsystem images'20077,149,821'Predictably defining input/output configurations for environments employing fabrics'20067,146,482'Memory mapped input/output emulation'20067,130,938'Method, system and program products for identifying communications adapters of a computing environment'20067,127,599'Managing configurations of input/output system images of an input/output subsystem, wherein a configuration is modified without restarting the input/output subsystem to effect a modification'20066,996,638'Method, system and program products for enhancing input/output processing for operating system images of a computing environment'20065,712,974'Method and apparatus for controlling the configuration definitions in a data processing system with a plurality of processors'19985,386,512'System for deriving and testing mutual capability set after receiving updated capability from other processors and before requesting service information'19955,349,675'System for directly displaying remote screen information and providing simulated keyboard input by exchanging high level commands'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2021Patents assigned to IBM (158)· patent assignee history
1994–2021Based in Poughkeepsie, NY, US· patent location history
2011–2016Patents assigned to GAINEY JR CHARLES W (35)· patent assignee history
2011–2016Patents assigned to OSISEK DAMIAN L (12)· patent assignee history
2011–2015Patents assigned to GREINER DAN F (11)· patent assignee history
2012–2016Patents assigned to FARRELL MARK S (14)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM1581994–2021
GAINEY JR CHARLES Wself352011–2016
FARRELL MARK S142012–2016
OSISEK DAMIAN L122011–2016
GREINER DAN F112011–2015
Locations
LocationPatentsSpan
Poughkeepsie, New York, US1661994–2021