USPatentGranted
B2

Formation of TSV backside interconnects by modifying carrier wafers

Granted 24 Jan 2012 · 4 office actions

Life of the patent

12 dated events
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Abstract

An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×10 8 Ohm-cm.

Claims

16 · 3 independent · depth 3
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16 granted claims

Classifications

3 codes
IPC · International Patent Classification
Section H — Electricity
  • H01L21/30
USPC · US Patent Classification
438/455438/459

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File wrapper

⤢ drag to zoomApr 2010Jul 2010Oct 2010Jan 2011Apr 2011Jul 2011Oct 2011Jan 2012USPTOApplicantNon-final rejectionResponse after non-finalResponse after finalRequest for continued examination
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Pendency
1.8 y
664 days filing → grant
Office actions
2
non-final + final
Responses
2
1 RCE
Examiner
Scott B Geyer
art unit 2812 · TC 2800
Citations: 22 back · 7 forward

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Term & fees

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Priority chain

2 priority documents
Priority
26 Jun 2009
earliest claimed
›Priority documents — 2
TypeDocumentDate
provisionalUS 6122080326 Jun 2009
related publicationUS 20100330798 A130 Dec 2010

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Citations

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