Inventor

Chen-Shien Chen

Inventor

Zhubei City, TW

Overview

2006–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 286 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1041%

H01LSemiconductor devices31%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%

H10DInorganic electric semiconductor devices5%

Y10TTechnical subjects covered by former us classification4%

H05KPrinted circuits2%

Y02PClimate change mitigation technologies in the production or processing of goods1%

H01FMagnets1%

H10BElectronic memory devices1%

B24BMachines, devices, or processes for grinding or polishing0%

PatentTitleYear

10,879,228Packaging mechanisms for dies with different sizes of connectors2020 10,867,810Substrate pad structure2020 10,868,106Semiconductor structure and method2020 10,867,976Semiconductor packages having dummy connectors and methods of forming same2020 10,861,811Connector structure and method of forming same2020 10,854,5773D die stacking structure with fine pitches2020 10,847,493Bump-on-trace interconnect2020 10,833,033Bump structure having a side recess and semiconductor structure including the same2020 10,811,377Package structure with a barrier layer and method for forming the same2020 10,797,005Semiconductor package and method for manufacturing the same2020 10,784,223Elongated bump structures in package structure2020 10,756,162Structure and formation method of semiconductor device with magnetic element2020 10,748,810Method of manufacturing an integrated inductor with protections caps on conductive lines2020 10,748,785Substrate pad structure2020 10,741,477Semiconductor devices and methods of forming the same2020 10,734,347Dummy flip chip bumps for reducing stress2020 10,720,788Wireless charging devices having wireless charging coils and methods of manufacture thereof2020 10,720,487Structure and formation method of semiconductor device with magnetic element2020 10,700,025Fan-out interconnect structure and method for forming same2020 10,692,828Package structure with protrusion structure2020 10,692,848Stress reduction apparatus and method2020 10,651,142Micro-connection structure and manufacturing method thereof2020 10,643,861Methods for making multi-die package with bridge layer2020 10,629,580Packaging mechanisms for dies with different sizes of connectors2020 10,573,573Package and package-on-package structure having elliptical conductive columns2020 10,546,845Package on package structure2020 10,535,593Package structure having a plurality of conductive balls with narrow width for ball waist2020 10,522,526LTHC as charging barrier in InFO package formation2019 10,522,382Method of manufacturing a semiconductor device2019 10,515,938Package on-package (PoP) device with integrated passive device in a via2019 10,515,919Bump-on-trace design for enlarge bump-to-trace distance2019 10,515,917Bump on pad (BOP) bonding structure in semiconductor packaged device2019 10,510,734Semiconductor packages having dummy connectors and methods of forming same2019 10,510,727Semiconductor device with discrete blocks2019 10,510,710Bump-on-trace interconnect2019 10,510,661Semiconductor devices and methods of forming the same2019 10,510,644Package structures and methods for forming the same2019 10,504,856Scheme for connector site spacing and resulting structures2019 10,483,225Packaging assembly and method of making the same2019 10,483,226Semiconductor device and method of forming the same2019 10,468,366Bonded structures for package and substrate2019 10,388,622Bump structure having a side recess and semiconductor structure including the same2019 10,388,620Connector structure and method of forming same2019 10,361,181Packaging mechanisms for dies with different sizes of connectors2019 10,354,931Packaging mechanisms for dies with different sizes of connectors2019 10,319,655POP structures with dams encircling air gaps and methods for forming the same2019 10,319,691Solderless interconnection structure and method of forming same2019 10,290,697Magnetic core inductor semiconductor structure and method2019 10,290,600Dummy flip chip bumps for reducing stress2019 10,283,471Micro-connection structure and manufacturing method thereof2019 10,276,481Package structure having a plurality of conductive balls having narrow width for the ball waist2019 10,276,548Semiconductor packages having dummy connectors and methods of forming same2019 10,276,525Package structure and method of fabricating the same2019 10,276,528Semicondcutor device and manufacturing method thereof2019 10,269,759Trace design for bump-on-trace (BOT) assembly2019 10,269,676Thermally enhanced package-on-package (PoP)2019 10,269,703Semiconductor device and method of forming the same2019 10,263,064Semiconductor devices and methods of forming the same2019 10,163,844Semiconductor device having conductive bumps of varying heights2018 10,163,873Package-on-package (PoP) device with integrated passive device in a via2018 10,163,781Semiconductor devices and methods of forming the same2018 10,163,839Bump on pad (BOP) bonding structure in semiconductor packaged device2018 10,163,827Package structure with protrusion structure2018 10,163,756Isolation structure for stacked dies2018 10,157,829Method for forming a passive device on a package-on-package structure2018 10,157,874Contact area design for solder bonding2018 10,157,8843D die stacking structure with fine pitches2018 10,153,243Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices2018 10,141,281Substrate and package structure2018 10,134,706Warpage control of semiconductor die package2018 10,128,195Substrate design with balanced metal and solder resist density2018 10,115,686Semiconductor structure and fabricating method thereof2018 10,084,032Semiconductor structure and method2018 10,056,345Conical-shaped or tier-shaped pillar connections2018 10,050,000Bump-on-trace structures with high assembly yield2018 10,043,774Integrated circuit packaging substrate, semiconductor package, and manufacturing method2018 10,037,973Method for manufacturing semiconductor package structure2018 10,020,276Protrusion bump pads for bond-on-trace processing2018 10,008,459Structures having a tapering curved profile and methods of making same2018 10,008,479Semiconductor device with discrete blocks2018 9,991,190Packaging with interposer frame2018 9,991,218Connector structures of integrated circuits2018 9,991,224Bump-on-trace interconnect having varying widths and methods of forming same2018 9,966,346Bump structure and method of forming same2018 9,953,939Conductive contacts having varying widths and method of manufacturing same2018 9,935,073Semiconductor structure and manufacturing method of the same2018 9,935,081Hybrid interconnect for chip stacking2018 9,917,035'Bump-on-trace interconnection structure for flip-chip packages'2018 9,911,725'Packaging mechanisms for dies with different sizes of connectors'2018 9,905,524'Bump structures in semiconductor device and packaging assembly'2018 9,881,885'Metal routing architecture for integrated circuits'2018 9,871,013'Contact area design for solder bonding'2018 9,859,252'Cooling channels in 3DIC stacks'2018 9,837,346Packaging device having plural microstructures disposed proximate to die mounting region2017 9,837,289Methods for forming package-on-package structures having buffer dams2017 9,824,992'Bump structure having a side recess and semiconductor structure including the same'2017 9,812,405'Semiconductor package and manufacturing method of the same'2017 9,799,620'Warpage reduction and adhesion improvement of semiconductor die package'2017 9,786,540'Method of manufacturing a semiconductor device'2017 9,786,621'Elongated bump structures in package structure'2017 9,773,755'Substrate interconnections having different sizes'2017 9,773,749'Warpage control of semiconductor die package'2017 9,768,138'Improving the strength of micro-bump joints'2017 9,761,503'Packaging mechanisms for dies with different sizes of connectors'2017 9,748,188'Method of forming a bump on pad (BOP) bonding structure in a semiconductor packaged device'2017 9,748,216'Apparatus and method for a component package'2017 9,741,589'Substrate pad structure'2017 9,735,130'Chip packages and methods of manufacture thereof'2017 9,721,918'Contact area design for solder bonding'2017 9,711,477'Dummy flip chip bumps for reducing stress'2017 9,679,862'Semiconductor device having conductive bumps of varying heights'2017 9,679,836'Package structures and methods for forming the same'2017 9,673,174'Through silicon via bonding structure'2017 9,673,125'Interconnection structure'2017 9,673,161'Bonded structures for package and substrate'2017 9,666,530'Semiconductor device'2017 9,659,903'Method of manufacturing connector structures of integrated circuits'2017 9,659,918'POP structures with dams encircling air gaps and methods for forming the same'2017 9,646,923'Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices'2017 9,646,943'Connector structure and method of forming same'2017 9,646,894'Packaging mechanisms for dies with different sizes of connectors'2017 9,640,521'Multi-die package with bridge layer and method for making the same'2017 9,633,965'Semiconductor structure and manufacturing method of the same'2017 9,620,414'Protecting flip-chip package using pre-applied fillet'2017 9,613,917'Package-on-package (PoP) device with integrated passive device in a via'2017 9,607,959'Packaging device having plural microstructures disposed proximate to die mounting region'2017 9,607,936'Copper bump joint structures with improved crack resistance'2017 9,589,861'Semiconductor packaging having warpage control and methods of forming same'2017 9,583,367'Methods and apparatus for bump-on-trace chip packaging'2017 9,576,821'Package structures including a capacitor and methods of forming the same'2017 9,559,069'Semiconductor device, integrated circuit structure using the same, and manufacturing method thereof'2017 9,543,278'Semiconductor device with discrete blocks'2017 9,536,850'Package having substrate with embedded metal trace overlapped by landing pad'2017 9,520,379'Method of forming bump structure having a side recess and semiconductor structure including the same'2016 9,508,668'Conductive contacts having varying widths and method of manufacturing same'2016 9,508,637'Protrusion bump pads for bond-on-trace processing'2016 9,508,674'Warpage control of semiconductor die package'2016 9,496,233'Interconnection structure and method of forming same'2016 9,490,167'Pop structures and methods of forming the same'2016 9,484,317'Scheme for connector site spacing and resulting structures'2016 9,478,474'Methods and apparatus for forming package-on-packages'2016 9,472,525'Bump-on-trace structures with high assembly yield'2016 9,472,521'Scheme for connector site spacing and resulting structures'2016 9,449,941'Connecting function chips to a package to form package-on-package'2016 9,431,351'Semiconductor package and manufacturing method of the same'2016 9,425,136'Conical-shaped or tier-shaped pillar connections'2016 9,425,157'Substrate and package structure'2016 9,425,117'Substrate design with balanced metal and solder resist density'2016 9,418,969'Packaged semiconductor devices and packaging methods'2016 9,406,629'Semiconductor package structure and manufacturing method thereof'2016 9,397,059'Bonded structures for package and substrate'2016 9,379,032'Semiconductor packaging having warpage control and methods of forming same'2016 9,379,078'3D die stacking structure with fine pitches'2016 9,373,598'Connector structures of integrated circuits'2016 9,368,460'Fan-out interconnect structure and method for forming same'2016 9,355,933'Cooling channels in 3DIC stacks'2016 9,349,699'Front side copper post joint structure for temporary bond in TSV application'2016 9,343,442'Passive devices in package-on-package structures and methods for forming the same'2016 9,330,947'Methods for forming package-on-package structures having buffer dams'2016 9,318,458'Bump structure having a side recess and semiconductor structure including the same'2016 9,312,225'Bump structure for stacked dies'2016 9,312,230'Conductive pillar structure for semiconductor substrate and method of manufacture'2016 9,299,674'Bump-on-trace interconnect'2016 9,293,449'Methods and apparatus for package on package devices with reversed stud bump through via interconnections'2016 9,287,191'Semiconductor device package and method'2016 9,287,234'Dummy flip chip bumps for reducing stress'2016 9,269,688'Bump-on-trace design for enlarge bump-to-trace distance'2016 9,263,377'POP structures with dams encircling air gaps and methods for forming the same'2016 9,257,332'Through-assembly via modules and methods for forming the same'2016 9,257,385'Landing areas of bonding structures'2016 9,257,412'Stress reduction apparatus'2016 9,258,922'PoP structures including through-assembly via modules'2016 9,232,632'Methods and apparatuses for detecting registration offsets'2016 9,224,688'Metal routing architecture for integrated circuits'2015 9,219,046'Strength of micro-bump joints'2015 9,219,106'Integrated inductor'2015 9,209,149'Bump-on-trace structures with high assembly yield'2015 9,196,573'Bump on pad (BOP) bonding structure'2015 9,190,348'Scheme for connector site spacing and resulting structures'2015 9,165,796'Methods and apparatus for bump-on-trace chip packaging'2015 9,165,887'Semiconductor device with discrete blocks'2015 9,159,695'Elongated bump structures in package structure'2015 9,153,550'Substrate design with balanced metal and solder resist density'2015 9,142,500'Apparatus for lead free solder interconnections for integrated circuits'2015 9,142,533'Substrate interconnections having different sizes'2015 9,129,818'Semiconductor device having conductive pads and a method of manufacturing the same'2015 9,123,788'Bonded structures for package and substrate'2015 9,117,825'Substrate pad structure'2015 9,111,817'Bump structure and method of forming same'2015 9,105,533'Bump structure having a single side recess'2015 9,105,530'Conductive contacts having varying widths and method of manufacturing same'2015 9,093,332'Elongated bump structure for semiconductor devices'2015 9,093,440'Connector structures of integrated circuits'2015 9,087,832'Warpage reduction and adhesion improvement of semiconductor die package'2015 9,070,644'Packaging mechanisms for dies with different sizes of connectors'2015 9,064,881'Protecting flip-chip package using pre-applied fillet'2015 9,059,107'Packaging methods and packaged devices'2015 9,053,990'Bump interconnection techniques'2015 9,053,989'Elongated bump structure in semiconductor device'2015 9,040,350'Packaging and function tests for package-on-package and system-in-package structures'2015 9,035,461'Packaged semiconductor devices and packaging methods'2015 9,006,909'Solder mask shape for BOT laminate packages'2015 8,981,576'Structure and method for bump to landing trace ratio'2015 8,975,726'POP structures and methods of forming the same'2015 8,932,906'Through silicon via bonding structure'2015 8,928,114'Through-assembly via modules and methods for forming the same'2015 8,922,006'Elongated bumps in integrated circuit devices'2014 8,921,222'Pillar structure having a non-planar surface for semiconductor devices'2014 8,922,005'Methods and apparatus for package on package devices with reversed stud bump through via interconnections'2014 8,916,971'Multi-direction design for bump pad structures'2014 8,912,649'Dummy flip chip bumps for reducing stress'2014 8,901,736'Strength of micro-bump joints'2014 8,889,484'Apparatus and method for a component package'2014 8,883,628'Electrical connection structure'2014 8,871,609'Thin wafer handling structure and method'2014 8,866,285'Fan-out package comprising bulk metal'2014 8,859,424'Semiconductor wafer carrier and method of manufacturing'2014 8,853,853'Bump structures'2014 8,847,387'Robust joint structure for flip-chip bonding'2014 8,829,673'Bonded structures for package and substrate'2014 8,823,170'Apparatus and method for three dimensional integrated circuits'2014 8,816,507'Package-on-Package structures having buffer dams and method for forming the same'2014 8,803,319'Pillar structure having a non-planar surface for semiconductor devices'2014 8,772,950'Methods and apparatus for flip chip substrate with guard rings outside of a die attach region'2014 8,765,497'Packaging and function tests for package-on-package and system-in-package structures'2014 8,766,441'Methods and apparatus for solder on slot connections in package on package structures'2014 8,759,949'Wafer backside structures having copper pillars'2014 8,753,971'Dummy metal design for packaging structures'2014 8,736,050'Front side copper post joint structure for temporary bond in TSV application'2014 8,729,699'Connector structures of integrated circuits'2014 8,729,700'Multi-direction design for bump pad structures'2014 8,716,123'Method of forming an integrated circuit device'2014 8,716,131'Through silicon via layout'2014 8,664,041'Method for designing a package and substrate layout'2014 8,659,123'Metal pad structures in dies'2014 8,659,170'Semiconductor device having conductive pads and a method of manufacturing the same'2014 8,653,648'Zigzag pattern for TSV copper adhesion'2014 8,653,626'Package structures including a capacitor and methods of forming the same'2014 8,643,196'Structure and method for bump to landing trace ratio'2014 8,623,756'Reflow system and method for conductive connections'2014 8,624,376'Package-on-package structure without through assembly vias'2014 8,624,360'Cooling channels in 3DIC stacks'2014 8,598,030'Process for making conductive post with footing profile'2013 8,598,691'Semiconductor devices and methods of manufacturing and packaging thereof'2013 8,546,945'Pillar structure having a non-planar surface for semiconductor devices'2013 8,546,941'Multi-direction design for bump pad structures'2013 8,513,119'Method of forming bump structure having tapered sidewalls for stacked dies'2013 8,476,769'Through-silicon vias and methods for forming the same'2013 8,476,759'Electrical connection structure'2013 8,461,045'Bond pad connection to redistribution lines having tapered profiles'2013 8,426,256'Method of forming stacked-die packages'2013 8,334,170'Method for stacking devices'2012 8,318,596'Pillar structure having a non-planar surface for semiconductor devices'2012 8,299,616'T-shaped post for semiconductor devices'2012 8,288,872'Through silicon via layout'2012 8,278,152'Bonding process for CMOS image sensor'2012 8,241,963'Recessed pillar structure'2012 8,232,643'Lead free solder interconnections for integrated circuits'2012 8,227,924'Substrate stand-offs for semiconductor devices'2012 8,202,800'Method of forming through silicon via with dummy structure'2012 8,193,639'Dummy metal design for packaging structures'2012 8,178,970'Strong interconnection post geometry'2012 8,158,489'Formation of TSV backside interconnects by modifying carrier wafers'2012 8,158,456'Method of forming stacked dies'2012 8,101,499'Formation of TSV backside interconnects by modifying carrier wafers'2012 8,097,953'Three-dimensional integrated circuit stacking-joint interface structure'2012 8,049,323'Chip holder with wafer level redistribution layer'2011 8,049,327'Through-silicon via with scalloped sidewalls'2011 8,034,708'Structure and process for the formation of TSVs'2011 7,969,013'Through silicon via with dummy structure and method for forming the same'2011 7,956,442'Backside connection to TSVs having redistribution lines'2011 7,928,534'Bond pad connection to redistribution lines having tapered profiles'2011 7,919,406'Structure and method for forming pillar bump structure having sidewall protection'2011 7,871,860'Method of semiconductor packaging'2011 7,851,331'Bonding structures and methods of forming bonding structures'2010 7,842,548'Fixture for P-through silicon via assembly'2010 7,816,227'Tapered through-silicon via structure'2010 7,785,927'Multi-die wafer level packaging'2010 7,666,688'Method of manufacturing a coil inductor'2010 7,662,665'Method for fabricating a semiconductor package including stress relieving layer for flip chip packaging'2010 7,633,165'Introducing a metal layer between SiN and TiN to improve CBD contact resistance for P-TSV'2009 7,564,115'Tapered through-silicon via structure'2009 7,514,797'Multi-die wafer level packaging'2009 7,294,043'CMP apparatus and process sequence method'2007 7,118,451'CMP apparatus and process sequence method'2006 7,004,814'CMP process control method'2006

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2006–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (131)· patent assignee history

2006–2019Based in Hsinchu, TW· patent location history

2009–2020Based in Zhubei City, TW· patent location history

2010Based in Shin-Chu, TW· patent location history

2012–2017Patents assigned to CHEN CHEN-SHIEN (65)· patent assignee history

2012–2017Patents assigned to HSIAO CHING-WEN (24)· patent assignee history

2012–2017Patents assigned to KUO CHEN-CHENG (24)· patent assignee history

2012–2020Based in Hsinchu County, TW· patent location history

2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (151)· patent assignee history

2016Based in Zhuhai, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	151	2015–2020
TAIWAN SEMICONDUCTOR MFG	131	2006–2016
CHEN CHEN-SHIENself	65	2012–2017
HSIAO CHING-WEN	24	2012–2017
KUO CHEN-CHENG	24	2012–2017

Locations

Location	Patents	Span
Zhubei City, TW	240	2009–2020
Hsinchu County, TW	23	2012–2020
Hsinchu, TW	20	2006–2019
Zhuhai, CN	1	2016
Shin-Chu, TW	1	2010