Inventor
Kuo-Ching Hsu
Inventor
Chung-Ho, TW
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1033%
H01LSemiconductor devices20%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H05BElectric heating9%
G06FElectric digital data processing5%
B23KSoldering or unsoldering3%
G01RMeasuring electric variables2%
G02BOptical elements, systems or apparatus2%
H03KPulse technique2%
H04BTransmission1%
PatentTitleYear
10,665,4743D packages and methods for forming the same202010,276,532Three-dimensional chip stack and method of forming the same201910,276,525Package structure and method of fabricating the same201910,269,5843D packages and methods for forming the same201910,163,756Isolation structure for stacked dies20189,984,981Packages with interposers and methods for forming the same20189,760,670'Semiconductor device design methods and conductive bump pattern enhancement methods'20179,698,115'Three-dimensional chip stack and method of forming the same'20179,633,869'Packages with interposers and methods for forming the same'2017RE046330'Driving apparatus of light emitting diode and driving method thereof'20179,570,366'Passivation layer for packaged chip'20179,508,666'Packaging structures and methods with a metal pillar'20169,372,951'Semiconductor device design methods and conductive bump pattern enhancement methods'20169,355,980'Three-dimensional chip stack and method of forming the same'20169,349,699'Front side copper post joint structure for temporary bond in TSV application'20169,343,419'Bump structures for semiconductor package'20169,312,225'Bump structure for stacked dies'20169,299,649'3D packages and methods for forming the same'20168,901,735'Connector design for packaging integrated circuits'20148,871,609'Thin wafer handling structure and method'20148,759,949'Wafer backside structures having copper pillars'20148,736,050'Front side copper post joint structure for temporary bond in TSV application'20148,670,637'Optical clock signal distribution using through-silicon vias'20148,664,760'Connector design for packaging integrated circuits'20148,610,360'LED device and method for preventing soft-start flicker'20138,610,285'3D IC packaging structures and methods with a metal pillar'20138,558,229'Passivation layer for packaged chip'20138,513,119'Method of forming bump structure having tapered sidewalls for stacked dies'20138,476,769'Through-silicon vias and methods for forming the same'20138,461,883'Frequency generator'20138,461,045'Bond pad connection to redistribution lines having tapered profiles'20138,427,081'Driving apparatus of light emitting diode and driving method thereof'20138,344,661'LED device with simultaneous open and short detection function and method thereof'20138,288,969'Driving apparatus of light emitting diode and driving method thereof'20128,169,156'Control method capable of preventing flicker effect and light emitting device thereof'20128,158,489'Formation of TSV backside interconnects by modifying carrier wafers'20128,154,223'Driving apparatus of light emitting diode and driving method thereof'20128,138,691'Multi-channel driving circuit and driving method thereof'20128,134,304'Light source driving device capable of dynamically keeping constant current sink and related method'20128,101,499'Formation of TSV backside interconnects by modifying carrier wafers'20128,005,326'Optical clock signal distribution using through-silicon vias'20117,956,442'Backside connection to TSVs having redistribution lines'20117,928,534'Bond pad connection to redistribution lines having tapered profiles'20117,679,926'Capacitors with insulating layer having embedded dielectric rods'20107,633,165'Introducing a metal layer between SiN and TiN to improve CBD contact resistance for P-TSV'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2020Based in Chung-Ho, TW· patent location history
2011–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (21)· patent assignee history
2011–2019Based in Taipei, TW· patent location history
2012–2014Patents assigned to HSU KUO-CHING (19)· patent assignee history
2012–2017Patents assigned to NOVATEK MICROELECTRONICS CORP (10)· patent assignee history
2012–2013Patents assigned to CHANG TSUNG-HAU (8)· patent assignee history
2012–2017Based in Hsinchu, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (11)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 21 | 2011–2016 |
| HSU KUO-CHINGself | 19 | 2012–2014 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 11 | 2016–2020 |
| NOVATEK MICROELECTRONICS CORP | 10 | 2012–2017 |
| CHANG TSUNG-HAU | 8 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Chung-Ho, TW | 23 | 2009–2020 |
| Taipei, TW | 12 | 2011–2019 |
| Hsinchu, TW | 10 | 2012–2017 |