Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module

A circuit configured to be mounted on a memory module comprising a first number of ranks, each rank of the first number of ranks comprising a plurality of double-data-rate (DDR) memory devices that are configured to be activated concurrently with one another and separately from the DDR memory devices of the other ranks by a first number of chip-select signals for receiving and transmitting data having a bit width of the rank, the first number of ranks comprising a first number of DDR memory devices, the memory module configured to be operationally coupled to a computer system, the circuit configurable to:nreceive a set of signals comprising bank address signals, a second number of chip-select signals, and row/column address signals from the computer system, the received set of signals capable of controlling a second number of ranks of DDR memory devices that are configured to be activated concurrently with one another and separately from the DDR memory devices of the other ranks for receiving and transmitting data having a bit width of the rank, the second number of ranks comprising a second number of DDR memory devices, the second number of ranks smaller than the first number of ranks, the second number of chip-select signals smaller than the first number of chip-select signals, and the second number of DDR memory devices smaller than the first number of DDR memory devices;generate phase-locked clock signals in response to clock signals of the computer system, wherein the circuit is configurable to transmit the generated phase-locked clock signals to the DDR memory devices of the first number of ranks; andprovide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.

A circuit configured to be mounted on a memory module comprising a first number of ranks, each rank of the first number of ranks comprising a plurality of double-data-rate (DDR) memory devices that are configured to be activated concurrently with one another and separately from the DDR memory devices of the other ranks by a first number of chip-select signals for receiving and transmitting data having a bit width of the rank, the first number of ranks comprising a first number of DDR memory devices, the memory module configured to be operationally coupled to a computer system, the circuit comprising:nmeans for receiving a set of signals comprising bank address signals, a second number of chip-select signals, and row/column address signals from the computer system, the received set of signals capable of controlling a second number of ranks of DDR memory devices that are configured to be activated concurrently with one another and separately from the DDR memory devices of the other ranks for receiving and transmitting data having a bit width of the rank, the second number of ranks comprising a second number of DDR memory devices, the second number of ranks smaller than the first number of ranks, the second number of chip-select signals smaller than the first number of chip-select signals, and the second number of DDR memory devices smaller than the first number of DDR memory devices;means for generating phase-locked clock signals in response to clock signals of the computer system, the generated phase-locked clock signals configured to be transmitted to the DDR memory devices of the first number of ranks; andmeans for providing the first number of chip-select signals to the first number of ranks, wherein the means for providing the first number of chip-select signals is responsive to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.

A method of using a memory module comprising a first number of ranks, each rank of the first number of ranks comprising a plurality of double-data-rate (DDR) memory devices that are configured to be activated concurrently with one another and separately from the DDR memory devices of the other ranks by a first number of chip-select signals for receiving and transmitting data having a bit width of the rank, the first number of ranks comprising a first number of DDR memory devices, the memory module configured to be operationally coupled to a computer system, the method comprising:nproviding a circuit configured to be mounted on the memory module;using the circuit to receive a set of signals comprising bank address signals, a second number of chip-select signals, and row/column address signals from the computer system, the received set of signals capable of controlling a second number of ranks of DDR memory devices that are configured to be activated concurrently with one another and separately from the DDR memory devices of the other ranks for receiving and transmitting data having a bit width of the rank, the second number of ranks comprising a second number of DDR memory devices, the second number of ranks smaller than the first number of ranks, the second number of chip-select signals smaller than the first number of chip-select signals, and the second number of DDR memory devices smaller than the first number of DDR memory devices;using the circuit to generate phase-locked clock signals in response to received clock signals of the computer system, and transmitting the generated phase-locked clock signals to the DDR memory devices of the first number of ranks; andusing the circuit to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.