Inventor

Jayesh R. Bhakta

Inventor

Cerritos, CA, US

Overview

2001–2021

Patent span

Physics

Primary field (CPC G)

Patents· 73 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores29%

G06FElectric digital data processing27%

H05KPrinted circuits18%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%

Y02PClimate change mitigation technologies in the production or processing of goods7%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%

Y10TTechnical subjects covered by former us classification3%

H01RElectrically-conductive connections1%

PatentTitleYear

11,093,417Memory module with data buffering2021 11,016,918Flash-DRAM hybrid memory module2021 10,949,339Memory module with controlled byte-wise buffers2021 10,884,923Memory module with local synchronization and method of operation2021 10,860,506Memory module with timing-controlled data buffering2020 10,489,314Memory module with data buffering2019 10,380,022Hybrid memory module and system and method of operating the same2019 10,324,841Memory module with local synchronization2019 10,268,608Memory module with timing-controlled data paths in distributed data buffers2019 10,217,523Multi-mode memory module with data handlers2019 10,025,731Memory module and circuit providing load isolation and noise reduction2018 9,928,186'Flash-DRAM hybrid memory module'2018 9,921,762'Redundant backup using non-volatile memory'2018 9,858,215'Memory module with data buffering'2018 9,846,659Memory module and circuit providing load isolation and noise reduction2017 9,824,035'Memory module with timing-controlled data paths in distributed data buffers'2017 9,606,907'Memory module with distributed data buffers and method of operation'2017 9,563,587'Memory module with distributed data buffers and method of operation'2017 9,426,916'Arrangement of memory devices in a multi-rank memory module'2016 9,269,437'Isolation switching for backup memory'2016 9,158,684'Flash-DRAM hybrid memory module'2015 9,128,632'Memory module with distributed data buffers and method of operation'2015 9,037,809'Memory module with circuit providing load isolation and noise reduction'2015 9,037,774'Memory module with load reducing circuit and method of operation'2015 8,971,045'Module having at least one thermally conductive layer between printed circuit boards'2015 8,904,098'Redundant backup using non-volatile memory'2014 8,904,099'Isolation switching for backup memory'2014 8,880,791'Isolation switching for backup of registered memory'2014 8,874,831'Flash-DRAM hybrid memory module'2014 8,864,500'Electronic module with flexible portion'2014 8,782,350'Circuit providing load isolation and noise reduction'2014 8,756,364'Multirank DDR memory modual with load reduction'2014 8,689,064'Apparatus and method for self-test in a multi-rank memory module'2014 8,677,060'Isolation switching for backup of registered memory'2014 8,671,243'Isolation switching for backup memory'2014 8,599,634'Circuit and method for refreshing a memory module'2013 8,516,185'System and method utilizing distributed byte-wise buffers on a memory module'2013 8,516,187'Data transfer scheme for non-volatile memory module'2013 8,516,188'Circuit for memory module'2013 8,417,870'System and method of increasing addressable memory space on a memory board'2013 8,359,501'Memory board with self-testing capability'2013 8,345,427'Module having at least two surfaces and at least one thermally conductive layer therebetween'2013 8,301,833'Non-volatile memory module'2012 8,287,291'Circuit with flexible portion'2012 8,264,903'Systems and methods for refreshing a memory module'2012 8,154,901'Circuit providing load isolation and noise reduction'2012 8,081,537'Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module'2011 8,081,535'Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module'2011 8,081,536'Circuit for memory module'2011 8,072,837'Circuit providing load isolation and memory domain translation for memory module'2011 8,033,836'Circuit with flexible portion'2011 8,001,434'Memory board with self-testing capability'2011 7,965,579'Circuit providing load isolation and memory domain translation for memory module'2011 7,965,578'Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module'2011 7,916,574'Circuit providing load isolation and memory domain translation for memory module'2011 7,881,150'Circuit providing load isolation and memory domain translation for memory module'2011 7,864,627'Memory module decoder'2011 7,839,645'Module having at least two surfaces and at least one thermally conductive layer therebetween'2010 7,811,097'Circuit with flexible portion'2010 7,636,274'Memory module with a circuit providing load isolation and memory domain translation'2009 7,630,202'High density module having at least two substrates and at least one thermally conductive layer therebetween'2009 7,619,912'Memory module decoder'2009 7,532,537'Memory module with a circuit providing load isolation and memory domain translation'2009 7,442,050'Circuit card with flexible connection for memory module with heat spreader'2008 7,375,970'High density memory module using stacked printed circuit boards'2008 7,289,386'Memory module decoder'2007 7,286,436'High-density memory module utilizing low-density memory components'2007 7,254,036'High density memory module using stacked printed circuit boards'2007 6,930,900'Arrangement of integrated circuits in a memory module'2005 6,930,903'Arrangement of integrated circuits in a memory module'2005 6,873,534'Arrangement of integrated circuits in a memory module'2005 6,751,113'Arrangement of integrated circuits in a memory module'2004 6,222,739'High-density computer module with stacked parallel-plane packaging'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2021Based in Cerritos, CA, US· patent location history

2004–2021Patents assigned to NETLIST INC (69)· patent assignee history

2011–2014Patents assigned to BHAKTA JAYESH R (14)· patent assignee history

2011–2014Patents assigned to SOLOMON JEFFREY C (11)· patent assignee history

2012–2014Patents assigned to LEE HYUN (8)· patent assignee history

2012–2014Patents assigned to CHEN CHI-SHE (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
NETLIST INC	69	2004–2021
BHAKTA JAYESH Rself	14	2011–2014
SOLOMON JEFFREY C	11	2011–2014
LEE HYUN	8	2012–2014
CHEN CHI-SHE	5	2012–2014

Locations

Location	Patents	Span
Cerritos, California, US	73	2001–2021