Inventor
Jeffrey C. Solomon
Inventor
Irvine, CA, US
Overview
Patents· 36 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing32%
G11CStatic stores31%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use16%
H05KPrinted circuits13%
Y02PClimate change mitigation technologies in the production or processing of goods9%
PatentTitleYear
11,016,918Flash-DRAM hybrid memory module202110,372,551Hybrid memory system with configurable error thresholds and failure analysis capability201910,025,731Memory module and circuit providing load isolation and noise reduction20189,928,186'Flash-DRAM hybrid memory module'20189,921,762'Redundant backup using non-volatile memory'20189,858,215'Memory module with data buffering'20189,846,659Memory module and circuit providing load isolation and noise reduction20179,269,437'Isolation switching for backup memory'20169,158,684'Flash-DRAM hybrid memory module'20159,037,809'Memory module with circuit providing load isolation and noise reduction'20158,904,098'Redundant backup using non-volatile memory'20148,904,099'Isolation switching for backup memory'20148,880,791'Isolation switching for backup of registered memory'20148,874,831'Flash-DRAM hybrid memory module'20148,782,350'Circuit providing load isolation and noise reduction'20148,756,364'Multirank DDR memory modual with load reduction'20148,677,060'Isolation switching for backup of registered memory'20148,671,243'Isolation switching for backup memory'20148,516,187'Data transfer scheme for non-volatile memory module'20138,516,188'Circuit for memory module'20138,301,833'Non-volatile memory module'20128,154,901'Circuit providing load isolation and noise reduction'20128,081,535'Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module'20118,081,537'Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module'20118,081,536'Circuit for memory module'20118,072,837'Circuit providing load isolation and memory domain translation for memory module'20117,965,579'Circuit providing load isolation and memory domain translation for memory module'20117,965,578'Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module'20117,916,574'Circuit providing load isolation and memory domain translation for memory module'20117,881,150'Circuit providing load isolation and memory domain translation for memory module'20117,864,627'Memory module decoder'20117,636,274'Memory module with a circuit providing load isolation and memory domain translation'20097,619,912'Memory module decoder'20097,532,537'Memory module with a circuit providing load isolation and memory domain translation'20097,289,386'Memory module decoder'20077,286,436'High-density memory module utilizing low-density memory components'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2021Patents assigned to NETLIST INC (33)· patent assignee history
2007–2021Based in Irvine, CA, US· patent location history
2011–2014Patents assigned to SOLOMON JEFFREY C (11)· patent assignee history
2011–2014Patents assigned to BHAKTA JAYESH R (8)· patent assignee history
2012–2014Patents assigned to CHEN CHI-SHE (5)· patent assignee history
2012–2014Patents assigned to BHAKTA JAYESH (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NETLIST INC | 33 | 2007–2021 |
| SOLOMON JEFFREY Cself | 11 | 2011–2014 |
| BHAKTA JAYESH R | 8 | 2011–2014 |
| CHEN CHI-SHE | 5 | 2012–2014 |
| BHAKTA JAYESH | 3 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Irvine, California, US | 36 | 2007–2021 |