Nonvolatile semiconductor memory

A nonvolatile semiconductor memory comprising:nfirst and second memory cells having a stack gate structure provided with a floating gate and a control gate and being adjacent to each other in an extending direction of the control gate,wherein each of the floating gates of the first and second memory cells is comprised a first part, and a second part arranged on the first part, a width of the second part in an extending direction of the control gate being narrower than that of the first part;the first part is arranged between element isolation insulating layers with a stripe shape, and an upper surface of the element isolation insulating layer exists on the same position in height as an upper surface of the first part or on a lower position than the upper surface of the first part; anda first space between the first parts of the first and second memory cells is filled with one kind of an insulator, and the control gate is arranged at a second space between the second parts of the first and second memory cells via a dielectric material having a dielectric constant higher than a dielectric constant of the insulator; andthe first part is also arranged on the upper surface of the element isolation insulating layer, and a width of the first part in an extending direction of the control gate is wider than that of the element isolation insulating layer.

A NAND-type flash memory comprising:nfirst and second memory cells having a stack gate structure provided with a floating gate and a control gate and being adjacent to each other in an extending direction of the control gate;a first NAND cell unit having a first memory cell; anda second NAND cell unit having a second memory cell,wherein each of the floating gates of the first and second memory cells is comprised a first part, and a second part arranged on the first part, a width of the second part in an extending direction of the control gate being narrower than that of the first part,the first part is arranged between element isolation insulating layers with a stripe shape, and an upper surface of the element isolation insulating layer exists on the same position in height as the upper surface of the first part or on a lower position than the upper surface of the first part; anda first space between the first parts of the first and second memory cells is filled with one kind of an insulator, and the control gate is arranged at a second space between the second parts of the first and second memory cells via a dielectric material having a dielectric constant higher than a dielectric constant of the insulator; andthe first part is also arranged on the upper surface of the element isolation insulating layer, and a width of the first part in an extending direction of the control gate is wider than that of the element isolation insulating layer.