Enclosed ferroelectric stacked capacitor

This invention relates to semiconductor circuit memory storage devices and more particularly to a process to develop three-dimensional stacked cell capacitors using a PZT ferroelectric material as a storage cell dielectric for use in high-density dynamic random access memory (DRAM) arrays.

In dynamic semiconductor memory storage devices it is essential that the storage node capacitor retain an adequate charge or capacitance in spite of parasitic capacitances and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continue to increase for future generations of memory devices.

The ability to densely pack storage cells while maintaining required storage capabilities is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.

One method of maintaining, as well as increasing, storage node capacitance in densely packed memory devices is through the use of "stacked storage cell" design. With this technology, two layers of conductive material, such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer with a dielectric layer sandwiched between each poly layer. A cell constructed in this manner is known as a stacked capacitor cell (STC). Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with inter-plate insulative layers having a high dielectric constant.

However, it is difficult to obtain sufficient storage capacitance with a conventional STC capacitor as the storage electrode area is confined within the limits of its own cell area. Also, maintaining high dielectric breakdown characteristics between poly layers in the STC capacitor becomes a major concern once insulator thickness is appropriately scaled.

A paper submitted by Reza Moazzami et al., entitled "A Ferroelectric DRAM Cell for High-Density NVRAM's," IEEE ELECTRONIC DEVICE LETTERS, Vol. 11, No. 10, October 1990, pp. 455-456, herein incorporated by reference, discusses the use of a PZT ferroelectric material as a cell dielectric in a planar capacitor.

As discussed on pp. 455 in section B. DRAM Mode, a PZT ferroelectric material has been used as the storage cell's dielectric film. As stated and shown in FIG. 3a, pp. 455, very little degradation was observed in the small-signal capacitance after 10 10 read/write cycles.

The PZT ferroelectric material has a high dielectric constant very favorable for use as a storage cell dielectric, but as discussed in this article PZT has only been used experimentally in planar storage capacitors. The present invention employs using PZT ferroelectric for the storage cell dielectric in three-dimensional stacked capacitor technology and develops an existing stacked capacitor fabrication process to construct a PZT three-dimensional stacked capacitor cell that will allow denser storage cell fabrication with minimal increases of overall memory array dimensions.

The invention is directed to maximizing storage cell surface area in a high density/high volume DRAM (dynamic random access memory) fabrication process. An existing stacked capacitor fabrication process is modified to construct a three-dimensional double plate stacked capacitor enclosed by a ferroelectric material, referred to hereinafter as an (E)nclosed (F)erroelectric (S)tacked (C)apacitor or EFSC. The EFSC design defines a capacitor storage cell that in the present invention is used in a DRAM process, however it will be evident to one skilled in the art to incorporate these steps into other processes requiring memory cells such as VRAMs, EPROMs or the like.

After a silicon wafer is prepared using conventional process steps, the present invention develops the EFSC by creating a conductive storage node structure conforming to the wafer's topology formed by two adjacent digit lines running perpendicular to and over the top of three adjacent word lines. A PZT ferroelectric material is used as the storage cell dielectric allowing for increased capacitance while maintaining the surface area required for a conventional 3-dimensional storage cell.

FIG. 1 is a top planar view of a portion of an in-process wafer showing digit lines, word lines and storage capacitors;

FIG. 2 is a cross-sectional view through broken line 1--1 of FIG. 1;

FIG. 3 is a cross-sectional view through broken line 2--2 of FIG. 1;

FIG. 4 is a cross-sectional view of the in-process wafer portion of FIG. 3 following a conformal oxide deposition, a conformal tungsten deposition and planarization;

FIG. 5 is a cross-sectional view of the in-process wafer portion of FIG. 4 following patterning and etching of tungsten to form a storage node plate;

FIG. 6 is a cross-sectional view of the in-process wafer portion of FIG. 5 after a deposition of conformal dielectric followed by a dielectric space etch;

FIG. 7 is a cross-sectional view of the in-process wafer portion of FIG. 6 after a tungsten deposition and planarization followed by removal of the dielectric spacers;

FIG. 8 is a cross-sectional view of the in-process wafer portion of FIG. 7, following deposition of a PZT ferroelectric material; and

FIG. 9 is a cross-sectional view of the in-process wafer portion of FIG. 8, following a deposition of tungsten, thus completing the EFSC structure.

The invention is directed to maximizing storage cell capacitance in a high density/high volume DRAM fabrication process, in a sequence shown in FIGS. 1-9.

A silicon wafer is prepared using conventional process steps up to the point of defining a cell array. Capacitor fabrication will now follow.

The capacitor of each cell will make contact with a buried contact within the cell, while the capacitor will extend to the active area of an adjacent cell. Each active area within the array is isolated from one another by a thick field oxide and can be arranged in interdigitated columns and non-interdigitated rows. The active areas are used to form active MOS transistors that can be doped as NMOS or PMOS type FETs depending on the desired use.

FIG. 1 shows a top planar view portion of a completed multilayered memory array with the main building blocks comprising digit lines 11, word lines 12 and a storage node plate 13 of a EFSC.

As shown in FIG. 2, poly 22, covered with silicide 23 and dielectric 24 (either oxide or nitride) are patterned to serve as word lines 12. Word lines 12 are further isolated from one another as well as subsequent conductive layers by dielectric spacers 26 (also either oxide or nitride). Word lines 12 have been previously deposited over a thin layer of gate oxide 25 or a thick layer of field oxide 27. Dielectrics 24 and 26 may be deposited by chemical vapor deposition (CVD). Active areas 21 have been appropriately doped to a desired conductivity type which penetrates into the bulk silicon wafer 20, by conventional process steps. Now the wafer is ready for digit line formation that will run perpendicular to and over word lines 12.

As shown in FIG. 3, an oxide layer 31 is deposited over the entire wafer array surface followed by buried digit line contacts patterning and etch. The buried digit line contacts cannot be seen, as the cross-sectional view of 2--2 in FIG. 1 does not pass through the buried contacts. Following the etching of a digit line buried contact, blanket depositions of polysilicon 32, silicide 33 and dielectric 34 are performed respectively. Dielectric 34 can be either nitride or oxide and is deposited by chemical vapor deposition (CVD) which is preferred for its excellent conformity. The layers of polysilicon 32, silicide 33 and dielectric 34 are patterned and etched to serve as parallel digit lines 11. Polysilicon 32 has previously been conductively doped to electrically couple with silicide 33 to serve as the conductor for digit lines 11. Digit lines 11 run perpendicular to and over the top of word lines 12 that are shown in FIG. 2 and conform to the wafer surface resulting in a waveform-like topology running in both the digit line and word line directions. A second dielectric, such as nitride or oxide is now deposited (preferably by CVD), followed by an anisotropic etch to form vertical dielectric spacers 35.

Up to this point, process flow has followed that of an array comprising conventional stacked capacitor cells. From this point forward, the process is unique to an array having EFSC-type storage capacitors.

As shown in FIG. 4, digit lines 11 and their subsequent isolation layers are then covered with dielectric 41 to a preferred thickness of 500 to 2000 angstroms preferably by CVD. Dielectric 41 may be either a layer of oxide or nitride. Following dielectric 41 deposition, although not seen in this cross-sectional view, a buried contact to active area 21 is located by coating the wafer surface with a photoresist. Then after applying the appropriate photomask, a buried contact anisotropic etch provides a opening for access to active area 21. Once the buried contact is established a conformal conductive layer 42, such as tungsten of tungsten silicide is deposited thus making contact to active area 21. Conductive layer 42 is then planarized to obtain a flat wafer surface.

As shown in FIG. 5, conductive layer 42 (of FIG. 4) is patterned and etched to form a storage node plate 51 of the EFSC.

As shown in FIG. 6, a conformal dielectric layer has been deposited followed by an anisotropic etch to create dielectric spacers 61. The dielectric used to form dielectric spacers 61 can be materials such as oxide, nitride or polyimide.

As shown in FIG. 7, a conformal conductive layer is deposited and planarized to form conductive spacers 71. Once again, in the preferred embodiment conductive spacers can be tungsten or tungsten silicide. Following planarization of conductive spacers 71 a controlled isotropic etch is performed to remove the dielectric spacers 61 shown in FIG. 6.

As shown in FIG. 8, a dielectric material presenting a very high dielectric constant such as a PZT ferroelectric material (lead zirconate titanate or PbZr 0 .5 Ti 0 .5 O 3 ) is then applied preferentially by a sol-gel technique known by one skilled in the art. PZT materials are known to present dielectric constant values 100 to 300 times higher than that of generally used cell dielectrics such as Si 3 N 4 . Using a sol-gel coating or depositing technique allows the PZT material to fill in gaps made by the absence of dielectric spacers 61 (seen in FIG. 6) and cover conductive storage node plate 51 and conductive spacers 71. The PZT material will serve as a cell dielectric 81 for the EFSC by isolating storage node plate 51 from conductive spacers 71 and from a conductive layer to be deposited next.

As shown in FIG. 9, a conformal conductive layer (tungsten or tungsten silicide) is deposited and now serves as one capacitor cell plate 91. Conductive spacers 71 serve as a bottom cell plate by connecting to a top cell plate 91 at the array periphery of the EFSC storage capacitor. Cell plate 91 and conductive spacers 71 form double capacitor cell plates which then become a common cell plate to all EFSC storage capacitors in the array.

With the cell dielectric being PZT material a very high dielectric constant material is utilized thus increasing the storage capability of the storage node cell without increasing the area required for cell construction. This important feature will allow fabrication of similar cell structures using PZT for future generations of memory devices such as 64M and 256M DRAMs.

Throughout the preferred embodiment, tungsten or tungsten silicide is deposited to serve as conductive capacitor plates, however many materials that possess conductive qualities which can be deposited or sputtered, may be used in place of the tungsten or tungsten silicide if so desired. It is therefore, to be understood that although the present invention has been described with reference to a preferred embodiment, various modifications, known to those skilled in the art, may be made to the structures and process steps presented herein without departing from the invention as recited in the claims appended hereto.