LexDanaLexDanabeta
Inventor

Yauh-Ching Liu

Inventor
Boise, ID, US

Overview

65→
Patents
1991–2009
Patent span
Electricity
Primary field (CPC H)

Patents· 65 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices36%
H10DInorganic electric semiconductor devices27%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
B24BMachines, devices, or processes for grinding or polishing2%
G11CStatic stores2%
PatentTitleYear
7,485,961'Approach to avoid buckling in BPSG by using an intermediate barrier layer'20096,924,522'EEPROM transistor for a DRAM'20056,806,551'Fuse construction for integrated circuit structure having low dielectric constant dielectric material'20046,794,698'Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls'20046,770,947'Laser-breakable fuse link with alignment and break point promotion structures'20046,690,044'Approach to avoid buckling BPSG by using an intermediate barrier layer'20046,627,968'Integrated capacitor and fuse'20036,566,730'Laser-breakable fuse link with alignment and break point promotion structures'20036,566,171'Fuse construction for integrated circuit structure having low dielectric constant dielectric material'20036,495,426'Method for simultaneous formation of integrated capacitor and fuse'20026,472,715'Reduced soft error rate (SER) construction for integrated circuit structures'20026,442,061'Single channel four transistor SRAM'20026,413,848'Self-aligned fuse structure and method with dual-thickness dielectric'20026,391,755'Method of making EEPROM transistor for a DRAM'20026,369,418'Formation of a novel DRAM cell'20026,365,452'DRAM cell having a vertical transistor and a capacitor formed on the sidewalls of a trench isolation'20026,316,312'Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures'20016,259,146'Self-aligned fuse structure and method with heat sink'20016,218,276'Silicide encapsulation of polysilicon gate and interconnect'20016,177,328'Methods of forming capacitors methods of forming DRAM cells, and integrated circuits incorporating structures and DRAM cell structures'20016,177,699'DRAM cell having a verticle transistor and a capacitor formed on the sidewalls of a trench isolation'20016,175,129'Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures'20016,166,403'Integrated circuit having embedded memory with electromagnetic shield'20006,162,714'Method of forming thin polygates for sub quarter micron CMOS process'20006,090,661'Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls'20006,090,239'Method of single step damascene process for deposition and global planarization'20006,066,525'Method of forming DRAM capacitor by forming separate dielectric layers in a CMOS process'20006,061,264'Self-aligned fuse structure and method with anti-reflective coating'20006,037,233'Metal-encapsulated polysilicon gate and interconnect'20006,004,880'Method of single step damascene process for deposition and global planarization'19995,973,344'EEPROM transistor for a DRAM'19995,953,614'Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step'19995,933,738'Method of forming a field effect transistor'19995,905,280'Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures'19995,723,375'Method of making EEPROM transistor for a DRAM'19985,688,700'Method of forming a field effect transistor'19975,372,974'Approach to avoid buckling in BPSG by using an intermediate barrier layer'19945,371,701'Stacked delta cell capacitor'19945,321,649'Stacked delta cell capacitor'19945,321,648'Stacked V-cell capacitor using a disposable outer digit line spacer'19945,266,513'Method of making stacked W-cell capacitor'19935,262,343'DRAM stacked capacitor fabrication process'19935,236,855'Stacked V-cell capacitor using a disposable outer digit line spacer'19935,236,860'Lateral extension stacked capacitor'19935,234,858'Stacked surrounding wall capacitor'19935,234,855'Stacked comb spacer capacitor'19935,219,778'Stacked V-cell capacitor'19935,196,364'Method of making a stacked capacitor dram cell'19935,170,233'Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor'19925,155,057'Stacked v-cell capacitor using a disposable composite dielectric on top of a digit line'19925,139,974'Semiconductor manufacturing process for decreasing the optical refelctivity of a metal layer'19925,122,476'Double DRAM cell'19925,108,943'Mushroom double stacked capacitor'19925,100,825'Method of making stacked surrounding reintrant wall capacitor'19925,089,986'Mushroom double stacked capacitor'19925,084,406'Method for forming low resistance DRAM digit-line'19925,084,405'Process to fabricate a double ring stacked cell structure'19925,082,797'Method of making stacked textured container capacitor'19925,081,559'Enclosed ferroelectric stacked capacitor'19925,061,650'Method for formation of a stacked capacitor'19915,057,888'Double DRAM cell'19915,053,351'Method of making stacked E-cell capacitor DRAM cell'19915,049,517'Method for formation of a stacked capacitor'19915,013,680'Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography'19914,981,810'Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers'1991

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1991–2009Patents assigned to MICRON TECHNOLOGY INC (40)· patent assignee history
1991–2009Based in Boise, ID, US· patent location history
1994Patents assigned to MICRON SEMICONDUCTOR INC (1)· patent assignee history
1999–2004Patents assigned to LSI LOGIC CORP (24)· patent assignee history
1999–2004Based in Sunnyvale, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC401991–2009
LSI LOGIC CORP241999–2004
MICRON SEMICONDUCTOR INC11994
Locations
LocationPatentsSpan
Boise, ID, US371991–2009
Sunnyvale, California, US281999–2004