Inventor

Hiang C. Chan

Inventor

Boise, ID, US

Overview

28→

Patents

1991–2001

Patent span

Electricity

Primary field (CPC H)

Patents· 28 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices38%

H10BElectronic memory devices34%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%

PatentTitleYear

6,197,662'Semiconductor processing method of forming field isolation oxide using a polybuffered mask which includes a base nitride layer on the substrate, and other semiconductor processing methods'2001 6,107,176'Method of fabricating a gate having a barrier of titanium silicide'2000 6,087,700'Gate having a barrier of titanium silicide'2000 5,966,621'Semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate'1999 5,798,296'Method of fabricating a gate having a barrier of titanium silicide'1998 5,358,894'Oxidation enhancement in narrow masked field regions of a semiconductor wafer'1994 5,313,087'Semiconductor device for minimizing diffusion of conductivity enhancing impurities from one region of a polysilicon layer to another'1994 5,281,549'Process for fabricating a stacked capacitor having an I-shaped cross-section in a dynamic random access memory array'1994 5,273,924'Method for forming an SRAM by minimizing diffusion of conductivity enhancing impurities from one region of a polysilicon layer to another region'1993 5,262,343'DRAM stacked capacitor fabrication process'1993 5,236,860'Lateral extension stacked capacitor'1993 5,236,856'Method for minimizing diffusion of conductivity enhancing impurities from one region of polysilicon layer to another region and a semiconductor device produced according to the method'1993 5,234,855'Stacked comb spacer capacitor'1993 5,170,233'Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor'1992 5,137,842'Stacked H-cell capacitor and process to fabricate same'1992 5,126,280'Stacked multi-poly spacers with double cell plate capacitor'1992 5,122,476'Double DRAM cell'1992 5,108,943'Mushroom double stacked capacitor'1992 5,089,986'Mushroom double stacked capacitor'1992 5,087,586'Process for creating fully-recessed field isolation regions by oxidizing a selectively-grown epitaxial silicon layer'1992 5,084,406'Method for forming low resistance DRAM digit-line'1992 5,084,405'Process to fabricate a double ring stacked cell structure'1992 5,082,797'Method of making stacked textured container capacitor'1992 5,081,559'Enclosed ferroelectric stacked capacitor'1992 5,061,650'Method for formation of a stacked capacitor'1991 5,057,888'Double DRAM cell'1991 5,053,351'Method of making stacked E-cell capacitor DRAM cell'1991 5,049,517'Method for formation of a stacked capacitor'1991

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1991–2001Patents assigned to MICRON TECHNOLOGY INC (28)· patent assignee history

1991–1994Based in Boise, ID, US· patent location history

1998–2000Based in Fremont, CA, US· patent location history

1999–2001Based in Freemont, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	28	1991–2001

Locations

Location	Patents	Span
Boise, ID, US	23	1991–1994
Fremont, California, US	3	1998–2000
Freemont, California, US	2	1999–2001