Semiconductor storage device and manufacturing method thereof

1. Field of the Invention

The present invention relates to a manufacturing method of semiconductor storage device, particularly to a manufacturing method of semiconductor storage device including storage node contacts.

2. Description of the Prior Art

Dynamic random access memory (DRAM) is a type of volatile storage device which is an indispensable key part of many electronic products. DRAM includes a great number of memory cells aggregated into an array for storing data, wherein each of the memory cells composed of a metal oxide semiconductor (MOS) transistor and a capacitor connected in series.

According to demands of products, the need to continuously increase the density of the memory cells in the array leads to more difficult and complex processes and design. Hence, industries keep making efforts to design new structures and/or processes in order to decrease the cost while increasing the yield under the limit of product standard.

The present invention provides a manufacturing method of semiconductor storage device, wherein storage node contacts are formed by first forming conductive patterns and then forming isolation patterns between the conductive patterns, so as to simplify manufacturing process and increase manufacturing yield.

According to an embodiment of the present invention, a manufacturing method of semiconductor storage device includes the following steps. First, a semiconductor substrate is provided, wherein the semiconductor substrate includes a plurality of active areas. Then, a plurality of bit line structures are formed on the semiconductor substrate, and a plurality of storage node contacts are formed between the plurality of bit line structures, wherein each of the storage node contacts is formed on one of the plurality of the active areas. The step of forming the storage node contacts includes forming a plurality of conductive patterns on the semiconductor substrate, wherein each of the conductive patterns straddles one of the bit line structures; and performing an etching back process to the conductive patterns for decreasing the thickness of the conductive patterns so as to form the storage node contacts. And a plurality of isolation patterns are formed between the plurality of conductive patterns, wherein the plurality of isolation patterns are formed after forming the plurality of conductive patterns and before the etching back process.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIGS. 1-14 are schematic diagrams illustrating a manufacturing method of a semiconductor storage device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along a cross-sectional line A-A′ of FIG. 1 .

FIG. 3 is a top view schematic diagram in a step subsequent to FIG. 1 .

FIG. 4 is a cross-sectional view taken along a cross-sectional line B-B′ of FIG. 3 .

FIG. 5 is a top view schematic diagram in a step subsequent to FIG. 3 .

FIG. 6 is a cross-sectional view taken along a cross-sectional line C-C′ of FIG. 5 .

FIG. 7 is a top view schematic diagram in a step subsequent to FIG. 5 .

FIG. 8 is a cross-sectional view taken along a cross-sectional line D-D′ of FIG. 7 .

FIG. 9 is a top view schematic diagram in a step subsequent to FIG. 7 .

FIG. 10 is across-sectional view taken along a cross-sectional line E-E′ of FIG. 9 .

FIG. 11 is a top view schematic diagram in a step subsequent to FIG. 9 .

FIG. 12 is a cross-sectional view taken along a cross-sectional line F-F′ of FIG. 11 .

FIG. 13 is a top view schematic diagram in a step subsequent to FIG. 11 .

FIG. 14 is a cross-sectional view taken along a cross-sectional line G-G′ of FIG. 13 .

Referring to FIGS. 1-14 , FIGS. 1-14 are schematic diagrams illustrating a manufacturing method of a semiconductor storage device according to a first embodiment of the present invention, in which FIG. 1 , FIG. 3 , FIG. 5 , FIG. 7 , FIG. 9 , and FIG. 13 are top view schematic diagrams, FIG. 2 is a cross-sectional view taken along a cross-sectional line A-A′ of FIG. 1 , FIG. 4 is a cross-sectional view taken along a cross-sectional line B-B′ of FIG. 3 , FIG. 6 is a cross-sectional view taken along a cross-sectional line C-C′ of FIG. 5 , FIG. 8 is a cross-sectional view taken along a cross-sectional line D-D′ of FIG. 7 , FIG. 10 is a cross-sectional view taken along a cross-sectional line E-E′ of FIG. 9 , FIG. 12 is a cross-sectional view taken along a cross-sectional line F-F′ of FIG. 11 , and FIG. 14 is a cross-sectional view taken along a cross-sectional line G-G′ of FIG. 13 . This embodiment provides a manufacturing method of a semiconductor storage device, including the following steps. First, as shown in FIG. 1 and FIG. 2 , a semiconductor substrate 10 is provided, and the semiconductor substrate 10 includes a plurality of active areas 12 . The semiconductor substrate 10 may include silicon substrate, epitaxial silicon substrate, silicon germanium substrate, silicon carbide substrate or silicon-on-insulator (SOI) substrate, but not limited thereto. A shallow trench isolation 11 is formed in the silicon substrate 10 and by which a plurality of active areas 12 are defined. The shallow trench isolation 11 can be formed by etching the semiconductor substrate 10 to form a plurality of trenches followed by filling the trenches with insulation materials such as silicon nitride or silicon oxynitride, but not limited thereto. In some embodiments, the shallow trench isolation 11 can be formed by other methods as needed. In addition, a plurality of word lines 22 can be formed in the semiconductor substrate 10 , and the word lines 22 in this embodiment can be buried word lines, but not limited thereto. The word lines 22 may be formed by being buried in the semiconductor substrate 10 and shallow trench isolation 11 . Agate dielectric layer 21 may be formed between the word lines 22 and the semiconductor substrate 10 , and a word line capping layer 23 may be formed to cover on the word lines 22 . The gate dielectric layer 21 , the word lines 22 and the word line capping layer 23 as mentioned above may be formed by first forming a plurality of trenches in the semiconductor substrate 10 and the shallow trenches isolation 11 followed by forming the gate dielectric layer 21 , the word lines 22 and the word line capping layer 23 sequentially in the trenches, but not limited thereto. In some embodiments, the gate dielectric layer 21 may include silicon oxide or other proper dielectric materials, the word lines 22 may include aluminum, tungsten, copper, titanium aluminide (TiAl) or other proper conductive materials, and the word line capping layer may include silicon nitride, silicon oxynitride, silicon carbonitride or other proper insulation materials.

And then, a plurality of bit line structures 30 are formed on the semiconductor substrate 10 . In some of the embodiments, each of the bit line structures 30 may extend along a first direction D 1 , each of the word lines 22 may extend along a second direction D 2 , and each of the active areas 12 may extend along an oblique direction different from the first direction D 1 and the second direction D 2 , but not limited thereto. Each of the bit line structures 30 is in contact with the corresponding active area 12 , and the bit line structures 30 may be electrically isolated from the non-corresponding active areas 12 through a dielectric layer 13 . Each bit line structure 30 may include a contact plug 31 , a low resistance layer 32 and a bit line capping layer 33 sequentially deposited in a vertical direction D 3 . The contact plug 31 may include silicon-containing conductive materials such as poly-silicon or amorphous silicon, the low resistance layer 32 may include materials with relatively low resistance such as aluminum, tungsten, copper, titanium aluminide or other proper low resistance materials, and the bit line capping layer 33 may include insulation materials such as silicon nitride, but not limited thereto. In addition, a barrier layer (not illustrated) may be disposed between the contact plug 31 and the low resistance layer 32 as needed. The materials of the barrier may include titanium, tungsten silicide (WSi), tungsten nitride (WN) or other proper barrier materials. Moreover, the bit line structures 30 may further include a spacer 34 formed on the side walls of the contact plugs 31 , the low resistance layer 32 and the bit line capping layer 33 .

Next, as show in FIG. 13 and FIG. 14 , a plurality of storage node contacts 40 C are formed between the plurality of bit line structures 30 , and each of the storage node contacts 40 C is formed on one of the plurality of the active areas 12 . In this embodiment, the step of forming the storage node contacts 40 C may include, but not limited to, the following steps. First, as shown in FIG. 7 and FIG. 8 , a plurality of conductive patterns 40 P are formed on the semiconductor substrate 10 , each of the conductive patterns 40 P straddles at least one of the plurality of bit line structures 30 . For instance, in this embodiment, each of the conductive patterns 40 P may extend along a second direction D 2 and straddles plural bit line structures 30 , but not limited thereto. In some embodiments, each of the conductive patterns 40 P may be formed with straddling only one bit line structure 30 . And then, as shown in FIG. 13 and FIG. 14 , an etching back process (such as the second etching back process 92 shown in FIG. 14 ) is performed to the conductive patterns 40 P for decreasing the thickness of the conductive patterns 40 P in the vertical D 3 and therefore the storage node contacts 40 C are formed.

The method of forming the conductive patterns 40 P of this embodiment may include, but not limited to, the following steps. First, as shown in FIG. 3 and FIG. 4 , a conductive layer 40 is formed on the semiconductor substrate 10 and the bit line structures 30 , and a portion of the conductive layer 40 is formed between plural bit line structures 30 . In this embodiment, the materials of the conductive layer 40 may include a silicon-containing conductive layer such as amorphous silicon layer, poly-silicon layer or other proper non-silicon conductive layer. It is worth mentioning that, before forming the conductive layer 40 , the other material layer on the active area 12 corresponding to the conductive patterns 40 P may be removed to expose a portion of the active area 12 , so as to make the conductive layer 40 be in contact with the corresponding active area 12 . And then, as shown in FIG. 5 to FIG. 8 , a patterning process to the conductive layer 40 is performed for forming the plurality of conductive layers 40 P, and a portion of each of the conductive patterns 40 P is formed between two of the plurality of bit line structures 30 adjacent to each other. In some of the embodiments, a patterned mask layer 49 may be formed on the conductive layer 40 , and the conductive patterns 40 P may be formed by performing an etching process to the conductive layer 40 by using the patterned mask layer 49 as an etching mask, but not limited thereto. In some the embodiments, the conductive patterns 40 P may be formed by performing other processes for patterning the conductive layer 40 as needed. In addition, the above mentioned etching process to the conductive layer 40 are preferably to have relatively low etching rate to the word line capping layer 23 and the shallow trench isolation 11 , so as to avoid the word lines 22 being affected by the etching process. However, some portions of the active areas 12 which are not covered by the conductive patterns 40 P may be partly etched by this etching process, but not limited thereto.

As shown in FIG. 13 and FIG. 14 , the manufacturing method of this embodiment may further include forming a plurality of isolation patterns 50 S between the conductive patterns 40 P, and the isolation patterns 50 S are formed after the step of forming the conductive patterns 40 P and before performing a second etching back process 92 . Specifically, the forming method of the isolation patterns 50 S may include, but not limited to, the following steps. First, as shown in FIG. 7 to FIG. 10 , an insulating layer 50 is formed on the semiconductor substrate 10 and the conductive patterns 40 P, and a portion of the insulating layer 50 is formed between plural conductive patterns 40 P. In other words, the insulating layer 50 is filled into the trenches 40 V between the conductive patterns 40 . The insulating layer 50 may include silicon nitride, silicon oxynitride, silicon carbonitride or other proper insulation materials. And then, as shown in FIG. 11 and FIG. 12 , a portion of the insulating layer 50 vertically laying on the conductive patterns 40 P in the vertical direction D 3 is removed, so as to expose the conductive patterns 40 P and form the isolation patterns 50 S. In some embodiments, the isolation patterns 50 S can be formed by removing the insulating layer 50 on the conductive patterns 40 P in the vertical direction D 3 through an etching back process (such as the first etching back process 91 shown in FIG. 12 ), but not limited thereto. In some other embodiments, the isolation patterns 50 S may be formed through other ways by removing the insulating layer 50 vertically laying on the conductive pattern 40 P in the vertical direction D 3 as needed, such as chemical mechanical polishing (CMP) process. In addition, because the isolation patterns 50 S are formed between the conductive patterns 40 P, the isolation patterns 50 S may extend along the second direction D 2 , and the word lines 22 may be covered by the isolation patterns 50 S in the vertical direction D 3 . Since the isolation patterns 50 S may be formed by filling the insulating layer 50 into the trenches between the conductive patterns 40 P and the trenches between the conductive layers 40 P expose the corresponding active areas 12 , each of the isolation patterns 50 S is directly in contact with at least one of the plurality of active areas 12 .

As shown in FIG. 11 to FIG. 14 , the second etching back process 92 is performed after forming the isolation patterns 50 S. In other words, the step of removing the insulating layer 50 on the conductive patterns 40 P is performed before the second etching back process 92 . In addition, the conductive patterns 40 formed on the bit line structures 30 in the vertical direction D 3 may also be removed by the second etching back process 92 . Hence, after the second etching back process 92 , a top surface of each storage node contact 40 C (such as the first top surface T 1 shown in FIG. 14 ) is lower than a top surface of each isolation pattern 50 S (such. as the second top surface T 2 shown in FIG. 14 ) and the top surface of each bit line structure 30 in the vertical direction D 3 . After that, a conductive structure (such as storage node contact pad, not illustrated) may be formed on each of the storage node contacts 40 C to electrically connected to the storage node contact 40 C. Metal silicide and/or barrier layer may be formed between the storage node contact pads and the storage node contacts 40 C, in order to decrease the contact resistance and/or avoid inter-diffusion between the materials that brings negative effects.

Furthermore, since it is preferable that the above-mentioned etching process used for forming the conductive patterns 40 P does not etch the shallow trench isolation 11 , the bottom surface of at least one of the plurality of storage node contacts 40 C (such as the first bottom surface B 1 shown in FIG. 14 ) and the bottom surface (such as the second bottom surface B 2 as shown in FIG. 14 ) of at least one of the plurality of isolation patterns 50 S (such as the isolation patterns 50 S formed on the shallow trench isolation 11 ) may be coplanar, but not limited thereto. Because the isolation patterns 50 S may be formed by filling the insulating layer 50 into the trenches between the conductive patterns 40 P with, each of the storage node contacts 40 C may be formed between two adjacent isolation patterns 50 S and may be directly in contact with these two isolation patterns 50 S. Besides, each of the storage node contacts 40 C is surrounded by two adjacent bit line structures 30 in the second direction D 2 and two adjacent isolation patterns 50 S in the first direction D 1 , and the conductive layer 40 used for forming the storage node contacts 40 C is formed after forming the bit line structures 30 , thus the width of each of the storage node contacts 40 C in the second direction D 2 can be defined by the distance between the two adjacent bit line structures 30 . In other words, the storage node contacts 40 C may be formed by a self-aligned method, and the bottom line width of the storage node contacts 40 C can thus be maximized.

To sum up the manufacturing method of the semiconductor storage device in this present invention, the storage node contacts are formed by first forming the conductive patterns and then forming the isolation patterns between the conductive patterns. Compare to the method of first forming isolation patterns and then filling the gaps of the isolation patterns with conductive patterns for forming storage node contacts, the manufacturing method of the present invention do not require forming a patterned oxide layer for defining the isolation patterns and thus the etching process for removing the patterned oxide layer is not needed, either. Hence the present invention can avoid negative effects on other material layers caused by the etching process for removing the patterned oxide layer. Based on the above reasons, the present invention brings the advantages of simplifying the manufacturing process and increasing the product yield of the process.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.