Semiconductor package device

This application claims the benefit of and priority to U.S. Provisional Application No. 62/289,524, filed Feb. 1, 2016, the content of which is incorporated herein by reference in its entirety.

1. Technical Field

The present disclosure relates to a semiconductor package device, and more particularly, to a semiconductor package device including light emitting components.

2. Description of the Related Art

Light Emitting Diodes (LEDs), or laser diodes, are widely used for many applications. A semiconductor light emitting device can include an LED chip having one or more semiconductor layers. The layers can be configured to emit coherent and/or incoherent light when energized. During manufacture, a large number of LED semiconductor dies can be produced on a semiconductor wafer. The wafer can be probed and tested to accurately identify particular color characteristics of each die, such as color temperature. Then, the wafer can be singulated to cut the wafer into a plurality of chips. The LED chips are typically packaged to provide external electrical connections, heat sinking, lenses or waveguides, environmental protection, and/or other features. Methods for making LED chip packages include processes such as die attach, wire bonding, encapsulating, testing, and others.

Some LED control circuits are used to generate a constant DC current through a string of a given number of LEDs. If it is desired to control each LED individually, a larger circuit board can be used to implement more complex circuits. It is useful in some cases to implement a leadframe with high quantities of leads for electrical connections.

In addition, in some lighting devices, multiple LEDs and a controller can individually molded and then mounted onto a mother board, which increases the manufacturing cost and the total size of the lighting devices.

In accordance with some embodiments of the present disclosure, an electronic device includes a carrier, a leadframe, a package body and a plurality of electronic components. The carrier has an open top surface, a closed bottom surface and sidewalls extending between the closed bottom surface and the open top surface. The carrier has a circular cavity in its open top surface extending toward the closed bottom surface. The carrier includes a leadframe including a die pad and a plurality of leads. The leads are physically isolated from the die pad by at least one gap. The package body partially encapsulates the leadframe such that a portion of an upper surface of the die pad and a portion of each of the leads are exposed from the package body. The exposed portions of the leads are arranged radially along the die pad. The electronic components are disposed on the die pad.

In accordance with some embodiments of the present disclosure, a carrier includes a leadframe and a package body. The leadframe includes a die pad and a plurality of leads. The leads are physically isolated from the die pad by at least one gap. The package body partially encapsulates the leadframe such that a portion of an upper surface of the die pad and a portion of each of the leads are exposed from the package body. The package body has an open top surface, a closed bottom surface and sidewalls extending between the closed bottom surface and the open top surface. The package body has a circular cavity in its open top surface extending toward the closed bottom surface. The exposed portions of the leads are arranged radially along the die pad.

In accordance with some embodiments of the present disclosure, an electronic module includes a first carrier. The first carrier includes a plurality of packages disposed thereon. Each package includes a second carrier. A case covers the packages. The second carrier has an open top surface, a closed bottom surface and sidewalls extending between the closed bottom surface and the open top surface. The second carrier has a circular cavity in its open top surface extending toward the closed bottom surface. The second carrier includes a leadframe, a package body and a plurality of electronic components. The leadframe includes a die pad and a plurality of leads. The leads are physically isolated from the die pad by at least one gap. The package body partially encapsulates the leadframe such that a portion of an upper surface of the die pad and a portion of each of the leads are exposed from the package body. The exposed portions of the leads are arranged radially along the die pad. The electronic components are disposed on the die pad.

FIG. 1A illustrates a perspective view of a semiconductor package device in accordance with some embodiments of the present disclosure.

FIG. 1B illustrates a bottom view of a semiconductor package device in accordance with some embodiments of the present disclosure.

FIG. 1C illustrates a schematic diagram of a semiconductor package device in accordance with some embodiments of the present disclosure.

FIG. 2 illustrates a top view of a semiconductor package device in accordance with some embodiments of the present disclosure.

FIG. 3 illustrates a top view of a semiconductor package device in accordance with some embodiments of the present disclosure.

FIG. 4 illustrates a schematic diagram of a semiconductor package device in accordance with some embodiments of the present disclosure.

FIG. 5 illustrates a top view of an electronic device in accordance with some embodiments of the present disclosure.

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. The present disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1A illustrates a perspective view of a semiconductor package device 1 in accordance with some embodiments of the present disclosure. The semiconductor package device 1 includes a carrier 10 and a plurality of electronic components 13 , 14 .

The carrier 10 has an open top surface, a closed bottom surface and sidewalls extending between the closed bottom surface and the open top surface. The carrier 10 has, or defines, a circular cavity 10 a in its open top surface extending toward the closed bottom surface. As shown in FIG. 1A , the carrier includes a leadframe 12 and a package body 11 .

The leadframe 12 is a pre-molded leadframe including a die pad 12 a and a plurality of leads 12 b . The leadframe 12 can be made of copper, copper alloy or another suitable metal or alloy. In some embodiments, the leadframe 12 may include one of, or a combination of the following: iron/iron alloy, nickel/nickel alloy, or any other metal/metal alloy. In some embodiments, the leadframe 12 is coated with a silver layer.

The die pad 12 a has a first area 12 a 1 and a second area 12 a 2 . In some embodiments, the first area 12 a 1 of the die pad 12 a is in a substantially arched or rounded shape. For example, the first area 12 a 1 of the die pad 12 a may have a circular shape, an oval shape or other arched shape. In some embodiments, the first area 12 a 1 of the die pad 12 a may be in the shape of at least a portion of a circle, oval, or other arched or rounded shape. In some embodiments, the die pad 12 a is a thermal pad that is able to withstand the thermal energy generated by the electronic components 13 , 14 disposed thereon (e.g. includes a suitable material for withstanding the thermal energy).

The leads 12 b are disposed radially along the die pad 12 a . For example, the leads 12 b may have a direction of longest extension that is in a direction from a center of the die pad 12 a towards an outer edge of the die pad 12 a . The leads 12 b are separated from the die pad 12 a . That is, there is a gap between each lead 12 b and the die pad 12 a . In some embodiments, at least one gap is filled by the package body 11 . In some embodiments, distances between the edge of the die pad 12 a and the end of at least two leads 12 b , some greater number of leads 12 b , or each lead 12 b are substantially the same. In some embodiments, a width of the gap is in a range from about 0.15 μm to about 0.2 μm. In some embodiments, the end of each lead is conformal with the edge of the die pad 12 a . In some embodiments, the leadframe 12 has thirteen leads. Alternatively, the leadframe 12 may have any number of leads, depending on requirements of the semiconductor package device.

The package body 11 is disposed on the leadframe 12 and covers a portion of the leadframe 12 . For example, the package body 11 covers a portion of the second area 12 a 2 of the die pad 12 a and a portion of the leads 12 b . In some embodiments, the package body 11 includes an epoxy resin having fillers dispersed therein.

The package body 11 has a circular cavity 10 a formed in its top surface extending toward its bottom surface, the cavity 10 a exposing a portion of the die pad 12 a and a portion of the leads 12 b . A sidewall 11 a of the cavity 10 a may be formed of materials which include reflective materials. In some embodiments, the sidewall 11 a of the cavity 10 a is used as a reflector. Since the electronic component 13 and the electronic component 14 are integrated into a single semiconductor package device 1 , it may be desirable to make the semiconductor package device smaller. The shape of the package body 11 can help to reduce the total size of the semiconductor package device 1 . For example, the package body 11 may include a recess 11 r to accommodate more components or to expose more leads. In some embodiments the recess 11 r is formed in the sidewall 11 a of the package body 11 .

The electronic components 13 , including 13 a , 13 b , 13 c , are disposed on the second area 12 a 2 of the die pad 12 a . In some embodiments, the electronic components 13 a , 13 b , 13 c are LEDs. The LEDs 13 a , 13 b , 13 c can be positioned in close proximity to each other. In some embodiments, such as for implementation in an “RGB” device, the three LEDs 13 a , 13 b , 13 c may be a red LED, a green LED and a blue LED respectively (e.g., emitting light respectively in a red frequency spectrum, a green frequency spectrum, and a blue frequency spectrum), and may be positioned in close proximity to each other for improved color mixing.

The electronic component 14 is disposed on the first area 12 a 1 of the die pad 12 a . In some embodiments, the electronic component 14 is a controller. The electronic component 14 can be or can include an integrated circuit (IC). The electronic component 14 may be a general purpose processor, microprocessor, or microcontroller, or another type of programmable component such as a field programmable gate array (FPGA), or other controller such as an application-specific IC (ASIC).

The electronic component 14 is electrically connected to the LEDs 13 a , 13 b , 13 c through conductive wires 15 , and is configured to control the LEDs 13 a , 13 b , 13 c through at least the wires. The electronic component 14 is also connected to the leads 12 b through other conductive wires 15 . In comparison with directly connecting the LEDs 13 a , 13 b , 13 c to the leads 12 b , the length of the conductive wires can be reduced by connecting the LEDs 13 a , 13 b , 13 c to the electronic component 14 and then connecting the electronic component 14 to the leads, which can help to prevent a short circuit in the conductive wires 15 . In addition, the cost for manufacturing the conductive wires 15 can be reduced because of their shorter length.

In order to individually or collectively control the LEDs, a carrier may include or carry a sophisticated circuitry, which may require a large number of leads for electrical connections. In some embodiments, a carrier may include a square cavity, which can limit a number and layout of the leads and can also hinder bonding of conductive wires between the electronic components and the leads due to different distances between leads and connection pads of the electronic components. FIG. 1A shows a circular cavity 10 a , in which the leads 12 b are conformal with the edge of the circular die pad 12 a , which can help to increase the number of leads that can fit in the semiconductor package device 1 . In addition, since the shape and the size of each lead 12 b exposed from the package body 11 may be substantially the same, it can be simpler to bond the conductive wires 15 from the electronic component 14 to the leads. Thereby, the manufacturing cost and time can be reduced.

FIG. 1B illustrates a bottom view of a semiconductor package device 1 in accordance with some embodiments of the present disclosure. As shown in FIG. 1B , a portion of the die pads 12 a and the leads 12 b are covered by the package body 11 . The exposed portion of the die pads 12 a and the leads 12 b are substantially coplanar with the bottom surface of the package body 11 .

FIG. 1C illustrates a schematic diagram of a semiconductor package device 1 in accordance with some embodiments of the present disclosure. As shown in FIG. 1C , each lead 12 includes a first portion 12 b 1 encapsulated or covered by the package body 11 and a second portion 12 b 2 exposed from the package body 11 . The width of each lead 12 decreases in a direction toward the die pad 12 a . Although the total lengths of the leads 12 may be different, the lengths of the second portion 12 b 2 of each lead are substantially identical. In some embodiments in which the lengths of each lead 12 are different, a step 12 b 3 may be formed between the first portion 12 b 1 and the second portion 12 b 2 , thus making the lengths of the exposed portion (e.g., the second portion 12 b 2 ) of each lead 12 uniform.

FIG. 2 illustrates a schematic diagram of a semiconductor package device 2 in accordance with some embodiments of the present disclosure. The semiconductor package device 2 is similar to the semiconductor package device 1 shown in FIG. 1C except that lengths of the exposed portion of each lead are not all the same. For example, the length of the exposed portion of the lead 22 b 1 is less than that of the exposed portion of the lead 22 b 2 . In some embodiments, some leads (e.g., the lead 22 b 3 ) might be completely encapsulated or covered by the package body 11 . Therefore, the distances between each lead and the die pad 12 a are not all uniform, which may increase the difficulty of bonding conductive wires from the electronic component 14 to the leads. This is in contrast to the embodiments shown in FIG. 1C , where, since the shape and the length of each lead 12 b exposed from the package body 11 are substantially the same, it is simpler to bond the conductive wires from the electronic component 14 to the leads 12 b , which can help to reduce the manufacturing cost and time.

FIG. 3 illustrates a schematic diagram of a semiconductor package device 3 in accordance with some embodiments of the present disclosure. The semiconductor package device 3 is similar to the semiconductor package device 1 shown in FIG. 1C except that lengths of the exposed portion of each lead are not all the same, the carrier 30 has a square cavity 30 a in its open top surface extending toward the closed bottom surface, and the die pad 32 a is in a square shape. The cavity 30 a being square shaped may limit a number and layout of the leads, and bonding of conductive wires between the electronic components and the leads may also be hindered due to different distances between leads and connection pads of the electronic components. In contrast, by using a circular cavity 10 a as shown in FIG. 1C , the leads 12 b can be made conformal with the edge of the circular die pad 12 a , which could increase the number of leads that fit in the semiconductor package device. In addition, as shown in FIG. 3 , the distances between each lead and the die pad 32 a are not uniform, which may make it difficult to bond conductive wires from the electronic component 34 to the leads. In contrast, as shown in FIG. 1C , since the shape and the size of each lead 12 b exposed from the package body 11 are substantially the same, it is simpler to bond the conductive wires 15 from the electronic component 14 to the leads. Therefore, the manufacturing cost and time can be reduced.

FIG. 4 illustrates a schematic diagram of a semiconductor package device 4 in accordance with some embodiments of the present disclosure. The semiconductor package device 4 is similar to the semiconductor package device 1 shown in FIG. 1C , except that in FIG. 4 , the first area 42 a 1 of the die pad 42 a and the second area 42 a 2 of the die pad 42 a are separated. A gap exists between the first area 42 a 1 of the die pad 42 a and the second area 42 a 2 of the die pad 42 a . A width of the gap may be, for example, in a range from about 0.15 μm to about 0.2 μm.

The LEDs 13 a , 13 b , 13 c are disposed on the second area 42 a 2 of the die pad 42 a . The electronic component 14 is disposed on the first area 42 a 1 of the die pad 42 a . By separating the first area 42 a 1 and the second area 42 a 2 of the die pad 42 a , the thermal energy produced by the LEDs 13 a , 13 b , 13 c is less likely to adversely affect the electronic component 14 .

FIG. 5 illustrates a top view of an electronic device 5 in accordance with some embodiments of the present disclosure. In some embodiments, the electronic device 5 is an adjustable LED module. As shown in FIG. 5 , the electronic device 5 includes a plurality of the semiconductor package devices 1 shown in FIG. 1A . In some embodiments, the electronic device 5 may include a plurality of the semiconductor package device 2 , 3 or 4 shown in FIGS. 2-4 or a combination thereof, including combinations with the semiconductor package devices 1 . In some embodiments, the electronic device 5 may include any number of semiconductor package devices.

As used herein, the terms “substantially,” “substantial,” “approximately,” and “about” are used to denote and account for small variations. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, a thickness of a film or a layer being “substantially uniform” can refer to a standard deviation of less than or equal to ±10% of an average thickness of the film or the layer, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within μm of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane. Two surfaces or components can be deemed to be “substantially perpendicular” if an angle therebetween is, for example, 90°±10°, such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°. When used in conjunction with an event or circumstance, the terms “substantially,” “substantial,” “approximately,” and “about” can refer to instances in which the event or circumstance occurs precisely, as well as instances in which the event or circumstance occurs to a close approximation.

In the description of some embodiments, a component provided “on” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It can be understood that such range formats are used for convenience and brevity, and should be understood flexibly to include not only numerical values explicitly specified as limits of a range, but also all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It can be clearly understood by those skilled in the art that various changes may be made, and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus, due to variables in manufacturing processes and such. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it can be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.