Method and circuit for programming a multilevel non-volatile memory

1. Technical Field of the Invention

The present invention generally relates to programming nonvolatile memory, and more specifically to a method and a circuit for programming a multilevel nonvolatile memory.

2. Description of Related Art

A memory chip is an electronic part which is used by a computer to store a program or data. There are two basic types of memory chips, volatile memory chips and nonvolatile memory chips. A nonvolatile memory chip, such as an EPROM or flash memory, does not lose its contents when power is switched off, while a volatile memory chips loses its contents when power is removed. It is known that most recent developments in the field of nonvolatile memories are directed towards increasing the storage capacities thereof.

Programming of a nonvolatile memory cell includes applying a potential difference between the drain and source of the floating gate transistor of the memory cell in the presence of a high potential difference being applied between the control gate and the source of the floating gate transistor. A known method used to program a multilevel nonvolatile memory utilizes a “voltage ladder” circuit, which is generated entirely inside the memory device. Moreover, in order to achieve effective programming, certain pins are dedicated for programming the memory cells. This limits the future expansion of the memory which generally requires an increasing number of address pins. Conventional memories use a chip enable pin Cen as a synchronization signal for the programming operation. However, the chip enable pin Cen may not be available in some nonvolatile memory devices for synchronizing programming operations.

In addition, the duration of time for programming the memory cells (i.e., the time for applying the programming voltages to a nonvolatile memory cell to the desired logic state) typically depends on complicated internal clock circuits whose delays are process dependent and varies considerably among individual devices.

Based upon the foregoing, there is a need for more effectively programming a multilevel nonvolatile memory device.

The present invention satisfies a significant need for more efficiently programming a multilevel nonvolatile memory. In accordance with an exemplary embodiment of the present invention, a multilevel nonvolatile memory is capable of being programmed without the use of dedicated programming pins. In addition, the memory does not require internal clock generation circuits to provide synchronization during a programming operation. Instead, the nonvolatile memory utilizes one or more address pins for providing synchronization during a programming operation.

A method of programming a nonvolatile memory cell according to the exemplary embodiment of the present invention may including comparing, using at least one address pin of the memory, a data value stored in an addressed nonvolatile memory cell to a desired data value, and applying, using the at least one address pin, program voltages to the addressed nonvolatile memory cell based upon the comparison.

A more complete understanding of the method and circuit of the present invention may be obtained by reference to the following Detailed Description when taken in conjunction with the accompanying drawings wherein:

FIG. 1 is a block diagram of a multilevel nonvolatile memory device according to an exemplary embodiment of the present invention;

FIG. 2 is a block diagram of the architecture of an internal data bus and a verification circuit of the memory device of FIG. 1;

FIG. 3 is a block diagram of a programming circuit used of the memory device of FIG. 1 .

FIGS. 4 a and 4 b are timing diagrams of the external and internal signals of the memory device during a programming operation; and

FIG. 5 is a flow diagram of a method for programming the multilevel nonvolatile memory of FIG. 1 .

The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which an exemplary embodiment of the present invention is shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiment set forth herein. Rather, the embodiment is provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Referring to FIG. 1, there is illustrated a multilevel nonvolatile memory device 50 according to an exemplary embodiment of the present invention. The memory device 50 includes at least one array 20 of memory cells organized into rows and columns of memory cells. The memory device 50 may further include row decode circuitry 22 which receives an externally generated address or portion thereof and selects and/or activates a row of memory cells in array 20 corresponding to the externally generated address.

Memory device may further include column decode circuitry 23 which receives an externally generated address or portion thereof and selects one or more columns of memory cells corresponding to the externally generated address. Column decode circuitry 23 may, for example, be implemented as multiplexing circuitry for connecting addressed column lines (not shown) to circuitry external to array 20 . In this way, the data contents of addressed memory cells, selected by row decode circuitry 22 and column decode circuitry 23 , are selectively provided for subsequent amplification during a memory access operation.

Memory device 50 may additionally include control circuitry 21 for receiving externally generated, input control signals and generally controlling the various components of memory device 50 to perform memory access operations. Control circuitry 21 may providing timing and other control signals to various circuitry within memory device 50 .

It is understood that the general use and operation of row and column decode circuitry in nonvolatile memory devices is known, so such circuitry will not be described in more detail for reasons of simplicity. It is further understood that memory device 50 may include other components or circuitry for performing memory access operations.

In addition, memory device 50 further includes blocks 100 and 200 demonstrating a verification circuit and programming circuit, respectively. Verification circuit 100 and programming circuit 200 are utilized for programming memory cells of array 20 , as will be described in more detail below.

Referring to FIG. 2, there is illustrated a block diagram of an internal data bus architecture and verification circuit 100 of memory device 50 . The verification circuit 100 comprises an internal data bus DATABUS used to store data to be programmed which arrives from the data output pads 35 of the memory device 50 . The verification circuit 100 is divided into a plurality of blocks designated by numerals 38 , 39 and 40 . For clarity, block designated as 38 is described in detail, however, blocks 39 and 40 are substantially the same as block 38 and operate in parallel to program three addressed memory cells at a time. It is understood that although verification circuit 100 is illustrated in FIG. 2 as having only three blocks 38 - 40 , verification circuit 100 may include any number of blocks in order to program any number of memory cells at a time.

Verification circuit 100 uses at least one and possibly two or more address pins for synchronizing programming operations. If two synchronization address pins are used, writing an entire array requires four consecutive sets of steps, with each set of steps used to program a quarter of the array 20 of memory cells. According to the exemplary embodiment of the present invention, each memory cell is capable of storing two bits of data (i.e., any one of four data levels). It is understood, however, that each memory cell may be capable of storing more than two bits of data.

Each block 38 , 39 and 40 comprises circuitry to verify the data stored in an addressed memory cell. For each block 38 - 40 , the data to be programmed arrives from the data output pads 35 of the memory and is stored temporarily at buffer 41 . The data from buffer 41 is transferred to the DATABUS from there the data is sent to a memory element 42 . The memory element 42 has an input, corresponding to the second address pin A 2 (i.e., the address pin corresponding to the second most significant bit of the input address), used for synchronization. The output from memory element 42 is passed to comparison logic 37 which is responsible for comparing the data to be programmed with the data outputted from a sense amplifier 36 used in amplifying the data value stored in the addressed memory cell. The comparison logic 37 compares the two sets of data to determine if the desired programming results are achieved. Once programming has occurred and a comparison made, the comparison logic 37 sends a signal STOPVPDLOC to a voltage source 43 to discontinue the application of a high voltage to the sense amplifier 36 . This removes the high voltage from the drain terminal of the memory cell and the corresponding addressed memory cell will not be further programmed as a result. Comparison logic 37 further generates a signal BLKPROGN used to control the programming of addressed memory cells during a programming operation, as described in greater detail below.

Referring to FIG. 3, there is illustrated a block diagram of a programming circuit 200 for programming a memory cell in accordance with the memory device 50 of FIG. 1 . To perform programming on each addressed memory cell, both an operational amplifier 53 (FIG. 3) and a voltage source 43 (FIG. 2) apply a high voltage to the gate and drain terminals, respectively, of an addressed memory cell. The ladder voltage required to program a multilevel memory cell is generated by a voltage divider 55 between a voltage Vpp and Vread which may be generated externally or internally relative to memory device 50 . Decoding logic 51 selects the desired voltage level from voltage divider 55 to be sent to the gate terminal of the addressed memory cells to be programed, using operational amplifier 53 . A counter 52 drives the decoding logic 51 and is controlled by two address pins A 1 and A 2 . Address pins A 1 and A 2 may be the two most significant bits of the input address pins of memory device 50 . During a programming operation, address pin A 2 serves to increment counter 52 and address pin A 1 selectively resets counter 52 . The counter 52 stores the number of programming pulses or intervals to be applied to the addressed memory cells being programmed. The counter 52 selects the voltage level from voltage divider 50 to be applied to the gate terminal of an addressed memory cell. Counter 52 is capable of counting through all of the possible states in programming the addressed memory cells. However, if the signal SETCOUNTER (generated by verification circuit 100 ) is asserted, counter 52 is put in the all 1 s state to provide an additional programming interval. The operation of counter 52 will be described in greater detail below.

FIGS. 4 a and 4 b illustrate the timing diagrams of external and internal signals of the memory device during a programming operation. FIG. 4 a illustrates the programming of a first and a second quarter of the memory array, while FIG. 4 b does the same for the third and fourth quarter of the memory array. The quarters of array 20 are identified by address pins A 1 and A 2 , as described below. The reference numeral 33 designates the preprogramming steps, while 34 designates the programming steps involved in programming the memory cell(s) in the specified quarter. The reference letter A refers to an address transition of all the addresses except A 1 and A 2 , which correspond to the two address pins used as the write synchronization signals during a programming operation. The signal PGMODE sets the memory for programming. Reference numeral 30 refers to the step of loading data in a buffer 41 , while 31 and 32 refer to reading data to be programmed and programming a memory cell, respectively. The signal ENDPROG indicates the end of programming and is outputted by counter 52 of FIG. 3 . The reference letters V and P along the second address pin A 2 indicates the verification and programming, respectively, of the programming operation. The verification and programming steps will be discussed in detail hereinafter with reference to FIG. 5 .

The timing diagram of FIG. 4 b is substantially similar to the timing diagram of FIG. 4 a , except that address pin A 2 is transitioned to the logic high state and then the logic low state during transit of the data on internal databus DATABUS. This allows programming of a different quarter of array 20 from the quarter programmed in FIG. 4 a.

Referring now to FIG. 5, there is illustrated a flow diagram describing the method of programming a memory in accordance with the exemplary embodiment of the present invention. Initially, it is assumed that the programming of memory cells in memory device 50 will be controlled/synchronized by two address bits, A 1 and A 2 . As a result, the programming of the memory cells in array 20 will occur in four sets of steps, with each set of steps corresponding to the programming of memory cells in a quarter of array 20 . It is understood, however, that a different number of address pins may be used to control/synchronize programming operations, thereby resulting in the programming of the memory cells occurring in a number of sets of steps other than four.

The memory programming mode is enabled using a signal PGMODE at step 1 . This step determines the active state of the memory by bringing a particular address of the memory to logic level high. Signal PGMODE may be, for example, the output of a latch controlled by address pins of memory device 50 . The addresses are set to logic level low at step 2 to identify the first quarter of array 20 , for example, and the supply voltage Vpp is raised to an elevated or high voltage at step 3 which stores in memory device 50 the value of the two address pins A 1 and A 2 at step 4 . At this point, address pins A 1 and A 2 may be used to synchronize or otherwise control a programming operation.

The address pin A 1 is brought to logic level high at step 5 . Together with the supply voltage Vpp being at an elevated voltage, step 5 causes a signal A 1 TLDUMMY to be asserted and counter 52 to be reset at step 6 . Step 7 performs the step of varying or transitioning the second synchronization address pin A 2 so that the data to be programmed are latched in memory element 42 on the falling edge of address pin A 2 at step 8 . The second synchronization address pin A 2 is then brought to the logic level high and functions hereafter as a clock, while the first synchronization address pin A 1 is brought to logic level low at step 9 . At this point, the preprogramming of memory device 50 is complete. In response to address pin A 1 being in the logic low state at step 9 , the output signal OUT in FIGS. 4 a and 4 b is brought to the logic level low at step 10 , and this low logic level of the OUT signal is an indication to the programmer that the programming stage has begun. Steps 1 - 9 refer to the pre-programming steps in accordance with the exemplary embodiment of the present invention.

The programming steps to program an addressed memory cell includes two verification steps, steps 12 and 14 . The actual programming begins with verification step 12 , which checks to see if the memory cell is programmed to the desired value. If the verification step 12 provides a negative response, the counter 52 is incremented at step 13 (via the occurrence of a triggering edge on address pin A 2 ) to apply a higher voltage to the addressed memory cell for application of a further programming interval on the addressed memory cell. Step 14 refers to the second verification step to determine if the memory cell has achieved its desired programming value. If the memory cell has not been programmed as desired, steps 12 - 13 are repeated. If after the second or other subsequent programming loop, the addressed memory cell has failed to be programmed, it is marked as a bad cell at step 15 . However, if the verification step at 12 yielded a positive result, programming ends by bring to the logic level high the output signal OUT as illustrated in FIGS. 4 a and 4 b at step 16 . The logic level high of the output signal OUT indicates the end of programming of the addressed memory cell.

If the desired programmed value is a 00 at step 17 (the data value loaded in step 8 ), the counter 52 is set to the all 1 's state at step 18 and another programming interval on the addressed memory cell is performed. This provides a maximum voltage to the gate terminal of the memory cell during the additional programming interval. This additional programming step is performed to increase noise margin. This additional programming step is performed upon each block 38 - 40 completing the programming of its corresponding addressed memory cell. In particular, when an addressed memory cell has been fully programmed as desired, signal BLKPROGN of the corresponding block 38 - 40 is set to the low logic state. When all of the blocks 38 - 40 set their corresponding signals BLKPROGN to the logic low state, signal SETCOUNTER is set to the high logic state, which sets counter 52 to be in the all Is state.

It is understood that steps 11 - 18 are performed for each addressed memory cell substantially simultaneously. In the case of memory device 50 having three blocks 38 - 40 , steps 11 - 18 is performed on the three addressed memory cells at substantially the same time.

Step 19 checks to see if the previously programmed memory cell(s) is (are) the last memory cell(s) to be programmed in the addressed quarter of the array. If step 19 provides a negative result, the address is incremented to point to the next memory cell(s) in the quarter of the array to be programmed at step 20 , after which steps 5 - 12 are repeated for programming the next memory cell(s) in the quarter. However, if all of the memory cells in the addressed quarter of the array have already been programmed, the method moves to step 21 , which verifies/determines if the current address is the last address for programming (i.e., if the memory cells in all four quarters of the array 20 have been programmed). If a positive response is received at step 21 , the programming cycle ends at step 22 . However, if the current address at step 21 is not the last address for programming, the high voltage is removed from Vpp at step 23 and the first and second synchronization address pins A 1 and A 2 are changed at step 24 to point to the next quarter of the array 20 to be programmed. Step 24 takes the method back to step 3 and the steps as discussed above are repeated for programming the memory cells in the newly addressed quarter of the array 20 .

Memory device 50 of the present invention advantageously provides effective synchronization during a programming operation by use of a relatively small number of address input pins and little circuit overhead, and without dedicated write/programming pins. Consequently, memory device 50 avoids the use of internal timing/clock circuitry that may vary considerably due to process dependencies.

Although preferred embodiments of the method and circuit of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it is understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications, and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.