Method of fabricating mask read only memory

This application claims the priority benefit of Taiwan application serial no. 90112760, filed on May 28, 2001.

1. Field of the Invention

The invention relates in general to a semiconductor process. More particularly, the invention relates to a method of fabricating a masked read only memory (MROM).

2. Description of the Related Art

The masked read only memory is the most basic structure and has the most simple fabrication process of the various kinds of read only memories. The memory cell of the masked read only comprises a MOS transistor. While programming, the channel region under the gate is implanted with ions to change the threshold voltage V T . In the masked read only memory, the data value is represented by the threshold voltage of the memory cell. By turning on/off the channel region of the memory cell under the gate, the data value is accessed. The on/off state is determined by the threshold voltage of the memory cell.

A conventional method of fabricating a mask read only memory is shown in FIGS. 1A to 1 C. In FIG. 1A, embedded bit lines 110 (perpendicular to the paper surface) and the isolation oxide layers 120 on the bit lines 110 are formed on the substrate 100 . A gate oxide layer 130 is formed over the substrate 100 . A word line 140 perpendicular to the bit lines 110 is formed. The substrate between a pair of the bit lines 110 and under the word line 140 is defined as a memory unit 144 .

In FIG. 1B, a coding step is performed. A photoresist layer 150 patterned with a coding window 153 that exposes a part of the memory unit 144 is formed. The coding window 153 has a width larger than the width of the memory unit 144 . The memory unit 144 is implanted with ions 160 to enhance the threshold voltage thereof. The coding process is complete.

In FIG. 1C, the photoresist layer 150 is removed, a dielectric layer is formed over the substrate 100 , and the subsequent process is performed.

In the above conventional method, as the coding window 153 in the photoresist layer 150 is wider than the memory unit 144 as shown in FIG. 2, the implanted ions 160 easily diffuse to positions outside the memory unit 144 . The threshold voltage and the channel threshold current are thus altered, thereby affecting the accuracy of data access.

The invention provides a method of fabricating a mask read only memory. Embedded bit lines are formed in a substrate. A gate dielectric layer and a word line are formed on the substrate. The substrate between a pair of the bit lines and under the word line is referred as a memory unit. A first dielectric layer is formed to cover the substrate. Several coding windows are formed in the first dielectric layers over a portion of the first dielectric layer. Spacers are formed on sidewalls of the coding windows. Using the first dielectric layer and the spacers as a mask, ions are implanted into the memory unit. A second dielectric layer is formed to fill the coding windows.

The invention further provides a programming method of a masked read only memory. After forming the bit lines and the word line across each other, a dielectric layer is formed to cover the substrate. A plurality of coding windows is formed in the first dielectric layer. The coding windows expose the memory units between two neighbouring bit lines and under the word line. Spacers are formed on sidewalls of the coding windows. Using the spacers and the first dielectric layer as a mask, the memory units under the coding windows are implanted with ions.

As mentioned above, spacers are formed on sidewalls of the coding windows in the invention. The ion implantation coverage is thus reduced. Ions are thereby prevented from diffusing to positions other than the memory units. Therefore, while programming the mask read only memory, the accuracy of data storage and access is not affected.

Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

FIGS. 1A to 1 C show a conventional method of fabricating a mask read only memory; and

FIGS. 2A to 2 F show the fabrication process of forming a mask read only memory according to the invention.

FIG. 2A to FIG. 2F show the fabrication process of a mask read only memory in one embodiment of the invention. In FIG. 2A, a pad oxide layer 202 , a mask layer 204 and a patterned photoresist layer 206 are formed on a substrate 200 in sequence. Using the photoresist layer 206 as a mask, the exposed photoresist mask layer 204 and the pad oxide layer 202 beneath are removed. Using the photoresist layer as a mask again, the exposed substrate 200 is doped to form embedded bit lines 210 .

In FIG. 2B, the photoresist layer 206 is removed, followed by a step of thermal oxidation. Isolation oxide layers 220 are thus formed by thermal oxidation of the exposed surface of the substrate 200 , and the bit lines 210 are thus covered thereby.

In FIG. 2C, the remaining mask layer 204 and the remaining pad oxide layer 202 are removed. A gate oxide layer 230 is formed on the substrate 200 . A word line 240 is formed perpendicularly across the bit lines 210 . The substrate 200 between two neighbouring bit lines 210 and under the word lines 240 are referred as the memory units 244 . A dielectric layer 270 is formed over the substrate 200 with a thickness of about 1000 Å to about 2000 Å. The dielectric layer 270 is planarized using chemical mechanical polishing (CMP), for example.

In FIGS. 2D and 2E, the coding process is performed. In FIG. 2D, a patterned photoresist layer 250 is formed over the substrate 200 . The photoresist layer 250 exposes a part of the dielectric layer 270 over memory units 244 . The exposed dielectric 270 is removed to form coding windows 273 therein.

In FIG. 2E, spacers 280 are formed on sidewalls of the coding windows 273 , such that the region to be implanted with ions is narrowed. The material of the spacers 280 comprises silicon oxide, for example. Ions 260 are implanted into the memory units 244 to raise the threshold voltage for coding. When the substrate 200 is a P-type substrate, the boron ions can be used in the implantation step.

In FIG. 2F, a dielectric layer 290 is formed to fill the coding windows 273 . A planarization step is performed on the dielectric layer using chemical mechanical polishing, for example.

According to the above, spacers are formed on sidewalls of the coding windows, so that the ion implanted range is shrunk to prevent the diffusion of ions towards positions outside the memory units. In addition, the invention performs the coding process after forming the dielectric layer, so that the number of the required photolithography processes is the same as that of the conventional method without affecting the turn around time (TAT).

Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.