Inventor
Cheng-Chen Calvin Hsueh
Inventor
Taipei, TW
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
Y10Sprimary
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests27%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
H10BElectronic memory devices18%
H10DInorganic electric semiconductor devices18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
C11DDetergent compositions3%
H01LSemiconductor devices3%
Y02PClimate change mitigation technologies in the production or processing of goods3%
PatentTitleYear
8,834,671'Apparatus and method for controlling silicon nitride etching tank'20148,409,997'Apparatus and method for controlling silicon nitride etching tank'20138,012,922'Wet cleaning solution'20118,012,846'Isolation structures and methods of fabricating isolation structures'20117,795,644'Integrated circuits with stress memory effect and fabrication methods thereof'20107,678,694'Method for fabricating semiconductor device with silicided gate'20106,998,316'Method for fabricating read only memory including a first and second exposures to a photoresist layer'20066,734,064'Method for fabricating read only memory including forming masking layers with openings and pre-coding the cell and peripheral regions'20046,670,247'Method of fabricating mask read only memory'20036,489,213'Method for manufacturing semiconductor device containing a silicon-rich layer'20026,468,897'Method of forming damascene structure'20026,448,136'Method of manufacturing flash memory'20026,444,521'Method to improve nitride floating gate charge trapping for NROM flash memory device'20026,136,687'Method of forming air gaps for reducing interconnect capacitance'20005,990,009'Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit'19995,981,356'Isolation trenches with protected corners'19995,859,458'Semiconductor device containing a silicon-rich layer'19995,854,503'Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit'19985,573,973'Integrated circuit having a diamond thin film trench arrangement as a component thereof and method'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2002Based in Sunnyvale, CA, US· patent location history
1998–2002Patents assigned to INTEGRATED DEVICE TECH (6)· patent assignee history
1999–2011Based in Taipei, TW· patent location history
2002–2006Patents assigned to MACRONIX INT CO LTD (6)· patent assignee history
2010–2014Patents assigned to TAIWAN SEMICONDUCTOR MFG (4)· patent assignee history
2011–2014Based in Lin-Kou, TW· patent location history
2013Patents assigned to CHIANG MING-TSAO CHIANG (1)· patent assignee history
2013Patents assigned to HSUEH CHENG-CHEN CALVIN (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEGRATED DEVICE TECH | 6 | 1998–2002 |
| MACRONIX INT CO LTD | 6 | 2002–2006 |
| TAIWAN SEMICONDUCTOR MFG | 4 | 2010–2014 |
| CHIANG MING-TSAO CHIANG | 1 | 2013 |
| HSUEH CHENG-CHEN CALVINself | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taipei, TW | 11 | 1999–2011 |
| Sunnyvale, California, US | 5 | 1996–2002 |
| Lin-Kou, TW | 3 | 2011–2014 |