Method of gettering layer for improving chemical-mechanical polishing process in flash memory production and semiconductor structure thereof

This invention relates to a method of gettering layer that can remove impurities or eliminate imperfections of element so as to improve chemical mechanical polishing process during flash-memory production.

The widely implemented nonvolatile memory may be divided into the categories including: read only memory (ROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash memory.

The low-price masked ROM is considered more profitable for mass production on the one hand, however, a vital loss beyond compensation might be resulted in the case of errors made in program or data on the other hand.

On the contrary, the high-cost EPROM can be programmed and erased repeatedly usually in some ten times, therefore, it would rather be fit for a small quantity production.

Programming or erasing of the EEPROM and flash memory can be performed by controlling charge or discharge of the gate. Efforts have been continuously made on the nonvolatile memory trying for further shortening the programming and the erasing time, lowering the working voltage and the device measurements, and lengthening the data preservable time.

The floating gate voltage (Vt) of the flash memory will drop down rapidly when it is baked around 250° C. because of the electrically combination of electrons and holes in the floating gate. As illustrated in FIG. 1, a conventional intermediate layer dielectric (ILD) of boron phosphor silicate glass (BPSG) is implemented for covering an element and serving as a gettering layer or a trapping layer so as to resist against moisture or catch mobile ions, wherein, for increasing flattening margin, the thickness of the ILD is determined subject to the pattern density so that the Vt may be affected after baking.

In order to improve the degraded reliability of a flash memory after baking, also the dielectrics of an intermediate layer dielectric (ILD) when flattening the margin of the dielectrics with chemical mechanical polishing (CMP), and enlargement of thickness margin of peripheral ILD and dense array, a method of gettering layer for improving chemical mechanical polishing process in flash-memory production is provided to protect a memory element against baking and keep its reliability by blockading mobile ion with the gettering layer. Moreover, by taking advantage of the gettering layer, reduction of the thickness of the ILD for increasing the etching margin, the deposition margin, and the remaining margin of oxides are made possible.

For realizing abovesaid objects, the method of gettering layer for improving chemical mechanical polishing process in flash-memory production comprises:

providing a substrate, whereon at least a memory structure layer is disposed;

depositing a first dielectric layer, which is formed lying on the memory structure layer;

depositing a gettering layer, which is formed lying on the first dielectric layer;

forming a second dielectric layer lying on the gettering layer; and

flattening the second dielectric layer with a chemical mechanical polisher.

For more detailed information regarding this invention together with advantages or features thereof, at least an example of preferred embodiment will be elucidated below with reference to the annexed drawings.

The related drawings in connection with the detailed description of this invention, which is to be made later, are described briefly as follows, in which:

FIG. 1 shows a conventional intermediate layer dielectric structure;

FIGS. 2 (A) through 2 (E) are schematic diagrams showing a method of gettering layer for improving chemical mechanical polishing process in flash-memory production;

FIG. 3 (A) shows a memory structure established according to an embodiment of this invention; and

FIG. 3 (B) indicates a plotted curve of test data of a memory element according to this invention and that of a conventional one respectively for comparison.

A method of gettering layer for improving chemical mechanical polishing (CMP) process in flash-memory production comprises:

providing a substrate 201 shown in FIG. 2 (A), whereon at least a memory structure layer 202 of AND, OR, or NAND gate element is disposed;

depositing a first dielectric layer 203 shown in FIG. 2 (B), which is formed lying on the memory structure layer 202 , and the material thereof may be undoped silicate glass (USG) or dielectrics otherwise;

depositing a gettering layer 204 shown in FIG. 2 (C), which is formed lying on the first dielectric layer 203 to enhance the reliability of the memory structure layer 202 , wherein the material of the gettering layer is an N—O—Si compound (SiO x N y ) formed by way of chemical vapor deposition (CVD) under conditions of: 300˜500° C., 4˜7 torr, and 100˜140W. When the thickness of the SiO x N y is 100˜1000 Å and the DUV is 248 Å, the value RI and K of the SiO x N y are found located between 1.9˜2.5 and 0.4˜0.7 respectively;

forming a second dielectric layer 205 shown in FIG. 2 (D) lying on the gettering layer 204 , wherein the second dielectric layer 205 may be phosphor silicate glass (PSG), boron phosphor silicate glass (BPSG), or dielectrics otherwise; and

flattening the second dielectric layer 205 shown in FIG. 2 (E) with a chemical mechanical polisher.

The intermediate gettering layer 204 between the dielectric layer of the USG 203 and BPSG 205 is arranged to blockade mobile ion so as to keep the reliability of the flash memory after baking. Moreover, as the SiO x N y layer is an excellent dielectric layer, reduction of the thickness of an intermediate layer dielectric (ILD) is possible for enlarging the margin of etching or grinding thereof and for improvement of the chemical mechanical polishing process applied to the ILD.

FIG. 3 (A) shows a memory structure according to this invention including a low-density peripheral structure on the left and a high-density array structure on the right. FIG. 3 (B) indicates a plotted curve of test data of a memory element according to this invention and that of a conventional one respectively for comparison, wherein:

SION-L and SION-R are test data of twin-cell element according to this invention when programmed at 9V or 7V and baked at 250° C. through 168 hours; and

STD-L and STD-R are test data of a conventional twin-cell element.

From the above, it is obvious that the element's floating gate voltage (Vt) of this invention may be changed in the range between 0.018˜0.06V when programmed at 9V or 7V, far below than 0.18V (up) of the conventional process when programmed at 9V, and such effect is more conspicuous when the programming voltage is higher.

In the above described, at least one preferred embodiment has been described in detail with reference to the drawings annexed, and it is apparent that numerous variations or modifications may be made without departing from the true spirit and scope thereof, as set forth in the claims below.