LexDanaLexDanabeta
Inventor

Kent Kuohua Chang

Inventor
Taipei, TW

Overview

82→
Patents
1999–2008
Patent span
Electricity
Primary field (CPC H)

Patents· 82 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices34%
H10BElectronic memory devices31%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
G11CStatic stores5%
C23CCoating metallic material2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
PatentTitleYear
7,408,220'Non-volatile memory and fabricating method thereof'20087,344,938'Method of fabricating memory'20087,229,876'Method of fabricating memory'20077,157,333'Non-volatile memory and fabricating method thereof'20077,098,096'Method of fabricating multi-bit flash memory'20067,009,245'High-K tunneling dielectric for read only memory device and fabrication method thereof'20066,979,619'Flash memory device and a method of fabrication thereof'20056,884,473'Method for fabricating metal silicide'20056,867,463'Silicon nitride read-only-memory'20056,858,506'Method for fabricating locally strained channel'20056,838,345'SiN ROM and method of fabricating the same'20056,831,851'Mask ROM'20046,812,099'Method for fabricating non-volatile memory having P-type floating gate'20046,812,521'Method and apparatus for improved performance of flash memory cell devices'20046,797,567'High-K tunneling dielectric for read only memory device and fabrication method thereof'20046,777,285'Memory device and method for fabricating the same'20046,777,742'Hexagonal gate structure for radiation resistant flash memory cell'20046,773,933'Method of boosting wafer cleaning efficiency and increasing process yield'20046,762,467'Nonvolatile memory cell for prevention of second bit effect'20046,737,324'Method for fabricating raised source/drain of semiconductor device'20046,720,613'Method of fabricating multi-bit flash memory'20046,713,388'Method of fabricating a non-volatile memory device to eliminate charge loss'20046,710,381'Memory device structure with composite buried and raised bit line'20046,706,612'Fabrication method for shallow trench isolation'20046,674,133'Twin bit cell flash memory device'20046,673,720'Method for improving the reliability of flash memories'20046,670,672'Structure of discrete NROM cell'20036,624,460'Memory device with low resistance buried bit lines'20036,620,698'Method of manufacturing a flash memory'20036,602,805'Method for forming gate dielectric layer in NROM'20036,599,801'Method of fabricating NROM memory cell'20036,589,835'Method of manufacturing flash memory'20036,580,639'Method of reducing program disturbs in NAND type flash memory devices'20036,566,203'Method for preventing electron secondary injection in a pocket implantation process'20036,551,879'Method for forming an oxide layer on a nitride layer'20036,548,425'Method for fabricating an ONO layer of an NROM'20036,541,322'Method for preventing gate depletion effects of MOS transistor'20036,538,292'Twin bit cell flash memory device'20036,500,711'Fabrication method for an interpoly dielectric layer'20026,498,104'Method of in-situ cleaning for LPCVD TEOS pump'20026,487,114'Method of reading two-bit memories of NROM cell'20026,486,028'Method of fabricating a nitride read-only-memory cell vertical structure'20026,461,949'Method for fabricating a nitride read-only-memory (NROM)'20026,458,212'Mesh filter design for LPCVD TEOS exhaust system'20026,455,890'Structure of fabricating high gate performance for NROM technology'20026,448,136'Method of manufacturing flash memory'20026,420,237'Method of manufacturing twin bit cell flash memory device'20026,413,840'Method of gettering layer for improving chemical-mechanical polishing process in flash memory production and semiconductor structure thereof'20026,410,949'Flash memory device with monitor structure for monitoring second gate over-etch'20026,380,029'Method of forming ono stacked films and DCS tungsten silicide gate to improve polycide gate performance for flash memory devices'20026,380,033'Process to improve read disturb for NAND flash memory devices'20026,376,309'Method for reduced gate aspect ratio to improve gap-fill after spacer etch'20026,362,049'High yield performance semiconductor process flow for NAND flash memory products'20026,355,522'Effect of doped amorphous Si thickness on better poly 1 contact resistance performance for nand type flash memory devices'20026,348,381'Method for forming a nonvolatile memory with optimum bias condition'20026,324,092'Random access memory cell'20016,323,047'Method for monitoring second gate over-etch in a semiconductor device'20016,309,927'Method of forming high K tantalum pentoxide Ta2O5 instead of ONO stacked films to increase coupling ratio and improve reliability for flash memory devices'20016,300,658'Method for reduced gate aspect ration to improve gap-fill after spacer etch'20016,284,602'Process to reduce post cycling program VT dispersion for NAND flash memory devices'20016,281,078'Manufacturing process to eliminate ONO fence material in high density NAND-type flash memory devices'20016,235,586'Thin floating gate and conductive select gate in situ doped amorphous silicon material for NAND type flash memory device applications'20016,221,164'Method of in-situ cleaning for LPCVD teos pump'20016,218,689'Method for providing a dopant level for polysilicon for flash memory devices'20016,204,159'Method of forming select gate to improve reliability and performance for NAND type flash memory devices'20016,184,084'Method to elimate silicide cracking for nand type flash memory devices by implanting a polish rate improver into the second polysilicon layer and polishing it'20016,180,454'Method for forming flash memory devices'20016,177,312'Method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of such device'20016,177,316'Post barrier metal contact implantation to minimize out diffusion for NAND device'20016,162,684'Ammonia annealed and wet oxidized LPCVD oxide to replace ono films for high integrated flash memory devices'20006,153,470'Floating gate engineering to improve tunnel oxide reliability for flash memory devices'20006,146,795'Method for manufacturing memory devices'20006,143,608'Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation'20006,140,246'In-situ P doped amorphous silicon by NH3 to form oxidation resistant and finer grain floating gates'20006,114,230'Nitrogen ion implanted amorphous silicon to produce oxidation resistant and finer grain polysilicon based floating gates'20006,074,917'LPCVD oxide and RTA for top oxide of ONO film to improve reliability for flash memory devices'20006,066,873'Method and apparatus for preventing P1 punchthrough'20006,063,666'RTCVD oxide and N.sub.2 O anneal for top oxide of ONO film'20006,063,668'Poly I spacer manufacturing process to eliminate polystringers in high density nand-type flash memory devices'20005,994,239'Manufacturing process to eliminate polystringers in high density nand-type flash memory devices'19995,981,339'Narrower erase distribution for flash memory by smaller poly grain size'19995,972,749'Method for preventing P1 punchthrough'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2005Patents assigned to ADVANCED MICRO DEVICES INC (37)· patent assignee history
1999–2005Based in Cupertino, CA, US· patent location history
2000–2001Patents assigned to FUJITSU LTD (2)· patent assignee history
2001–2008Patents assigned to MACRONIX INT CO LTD (44)· patent assignee history
2001Patents assigned to FUJITSU AMD SEMICONDUCTOR LTD (1)· patent assignee history
2001–2002Based in Tu-Cheng, TW· patent location history
2002–2008Based in Taipei, TW· patent location history
2003Patents assigned to MACRONIX INTERNAT CO INC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MACRONIX INT CO LTD442001–2008
ADVANCED MICRO DEVICES INC371999–2005
FUJITSU LTD22000–2001
FUJITSU AMD SEMICONDUCTOR LTD12001
MACRONIX INTERNAT CO INC12003
Locations
LocationPatentsSpan
Taipei, TW432002–2008
Cupertino, California, US371999–2005
Tu-Cheng, TW22001–2002