Method of forming self-aligned twin wells

(1) Field of the Invention

This invention relates to methods used to fabricate semiconductor devices and more specifically to a method used to form well regions for N channel, and for P channel, metal oxide semiconductor field effect transistors.

(2) Description of Prior Art

The advent of complimentary metal oxide semiconductor (CMOS), technology, featuring N channel (NFET), and P channel (PFET), devices, on the same semiconductor chip, created the need for twin wells, specifically an N well region to accommodate the PFET devices, and a P well region for the NFET devices. To satisfy density, as well as performance requirements, it is imperative that the twin well regions be self-aligned, minimizing the area needed for these regions, as well as minimizing the distance between the conductive structures used for communication between the different type devices. One method of satisfying the self-alignment requirement is the formation of a first well region, such as the N well region for the PFET or PMOS type devices, in a region of a semiconductor substrate exposed in an opening formed in an overlying silicon nitride layer. This is followed by an oxidation procedure which results in a thick silicon dioxide layer on the N well region, while silicon dioxide growth is retarded by the silicon nitride layer overlying a region of a lightly doped, P type semiconductor substrate, to be used to subsequently accommodate the P well region. After removal of the silicon nitride layer an ion implantation procedure is employed to place the P type ions, needed for formation of the P well region, into the portion of the semiconductor substrate not blocked by the thick silicon dioxide layer, located overlying the N well region, thus self-alignment of the twin wells is realized.

The present invention will describe a novel procedure for forming self-aligned, twin well regions, without the use of silicon nitride, thus reducing process costs, as well as avoiding the process complexity of depositing, patterning, and removing silicon nitride. This invention will feature the different oxidation rates of N type doped silicon, and lightly doped P type silicon, to achieve an non-silicon nitride procedure for formation of self-aligned twin wells. Prior art, such as Kim et al, in U.S. Pat. No. 5,766,970, as well as Schwabe et al, in U.S. Pat. No. 4,434,543, describe methods for obtaining self-aligned twin well regions, however these prior arts feature the use of a patterned, silicon nitride layer, to accomplish the self-aligned objective.

It is an object of this invention to form twin well regions, to accommodate CMOS designs comprised of PFET as well NFET devices.

It is another object of this invention to form the twin well regions for CMOS designs, employing procedures resulting in self-aligned twin well regions.

It is still another object of this invention to minimize fabrication cost, and reduce process complexity, via forming self-aligned twin well regions, without the use of a patterned silicon nitride layer, as an oxidation retarding mask.

In accordance with the present invention a method of forming self-aligned, twin well regions in a semiconductor substrate, via use of differential oxidation rates on specifically doped regions, without the use of a silicon nitride, oxidation retarding layer, is described. A photoresist shape is used as a mask to allow N type ions to be implanted into first region of the semiconductor substrate, exposed in an opening in the photoresist shape. A thermal oxidation procedure is then employed resulting a thick silicon dioxide formation, on the first region of the semiconductor substrate, with a N well region formed directly underlying the thick silicon dioxide layer. A thinner silicon dioxide layer is formed on second regions of the P type, semiconductor substrate. A second ion implantation procedure is performed to allow P type ions to be implanted through the thinner silicon dioxide layer, into second regions of the semiconductor substrate, while the thicker silicon dioxide layer prevents the P type implantation from entering the N well region. An anneal procedure is then used to activate the P type ions, resulting in P well regions located in second regions of the semiconductor substrate, self-aligned to the N well region, located in the first region of the semiconductor substrate.

The object and other advantages of this invention are best described in the preferred embodiment with reference to the attached drawings that include:

FIGS. 1-5, which schematically, in cross-sectional style, describe key stages of fabrication used to form self-aligned twin regions in a semiconductor substrate, via use of differential oxidation rates on specifically doped regions, without the use of a silicon nitride as an oxidation retarding layer.

The method of forming self-aligned twin regions in a semiconductor substrate, via use of differential oxidation rates, used to form thick and thin silicon dioxide regions, on specifically doped regions, without the use of a silicon nitride layer as an oxidation retarding layer, will now be described in detail. A P type, semiconductor substrate 1 , comprised of single crystalline silicon, with a < 100 > crystallographic orientation is used and schematically shown in FIG. 1 . Semiconductor substrate 1 , is comprised with a resistivity between about 8 to 12 ohm-cm. Silicon dioxide layer 2 a, is next formed at a thickness between about 150 to 250 Angstroms, via thermal oxidation procedures. Silicon dioxide layer 2 a, will be used as a pad or screen oxide layer to prevent heavy metal ions from entering portions of the underlying semiconductor substrate during subsequent ion implantation procedures, performed through silicon dioxide layer 2 a, into specific regions of semiconductor substrate 1 . Photoresist shape 3 , is next formed on silicon dioxide layer 2 a, with opening 4 , exposing a portion of semiconductor substrate 1 , (underlying silicon dioxide layer 2 a ), to be used to accommodate an N well region. A first ion implantation procedure is then performed, using arsenic or phosphorous ions, at an energy between about 80 to 120 KeV, and at a dose between about 4 E15 to 6 E15 atoms/cm 2 , resulting in N type layer 5 a, comprised of unactivated N type ions, located in a first region of semiconductor substrate 1 . This is schematically shown in FIG. 1 .

After removal of photoresist shape 3 , via plasma oxygen ashing and careful wet cleans, a thermal oxidation procedure is performed at a temperature between about 960 to 1000° C., in a oxygen—steam ambient. The thermal oxidation procedure results in the formation of silicon dioxide layer 6 , at a thickness between about 4500 to 5500 Angstroms, in the first region of semiconductor substrate 1 . The presence of N type layer 5 a, enhanced the oxidation rate, when compared to thicknesses obtained via thermal oxidation of less doped regions, resulting in the desired thickness of silicon dioxide layer 6 , as well as activating the N type ions, in N type layer 5 a, thus resulting in initial N well region 5 b, located directly underlying silicon dioxide layer 6 . The same thermal oxidation procedure also results in the growth of silicon dioxide layers 2 b, on second regions of semiconductor substrate 1 , to be subsequently used for P well regions. The lighter concentration of dopant in P type semiconductor substrate 1 , when compared to the heavier dopant concentration of N type layer 5 a, resulting in a thickness for silicon dioxide layers 2 b, between about 750 to 1250 Angstroms. The result of these procedures are schematically shown in FIG. 2 .

A second ion implantation procedure, using boron or BF 2 ions, at an energy between about 45 to 55 KeV, and at a dose between about 2E13 to 4E13 atoms/cm 2 , is next performed, through silicon dioxide layers 2 b, to create P type layer 7 a, in second portions of semiconductor substrate 1 , or in portions of semiconductor substrate 1 , not covered by silicon dioxide layer 6 . The thickness of silicon dioxide layer 6 , as well as the energy of the second ion implantation procedure, prevented implantation into the first region of semiconductor substrate 1 , or into initial N well region 5 b. In addition the blocking characteristics of thicker dioxide layer 6 , allowed self-alignment of P type layer 7 a, to initial N well region 5 b, to be realized. The result of this procedure is shown schematically in FIG. 3 .

An anneal procedure is next performed in either a conventional furnace, or via a rapid thermal anneal procedure, at a temperature between about 1000 to 1200° C., in an nitrogen or argon ambient, resulting in activation of the P type ions, in P type layer 7 a, creating P well regions 7 b. The same anneal procedure also results in additional drive-in for the N type dopants in initial N well region 5 b, resulting in final N well region 5 c. The self-alignment of P well regions 7 b, to final N well region 5 c, can be schematically observed in FIG. 4 . Finally silicon dioxide layer 6 , as well as silicon dioxide layer 2 b, are selectively removed via wet procedures using a dilute of buffered HF solution as an etchant. Final N well region 5 c, is now available to accommodate PFET devices, while P well regions 7 b, are now ready to accommodate the NFET elements of the CMOS device.

While this invention has been particularly shown and described with reference to, the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention.