Inventor
Shun-Liang Hsu
Inventor
Hsinchu, TW
Overview
Patents· 48 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices43%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests11%
B24BMachines, devices, or processes for grinding or polishing1%
G01BMeasuring length, thickness or similar linear dimensions1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
G11CStatic stores1%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%
PatentTitleYear
8,497,584'Method to improve bump reliability for flip chip device'20138,389,341'Lateral power MOSFET with high breakdown voltage and low on-resistance'20138,129,783'Lateral power MOSFET with high breakdown voltage and low on-resistance'20128,114,745'High voltage CMOS devices'20127,989,890'Lateral power MOSFET with high breakdown voltage and low on-resistance'20117,915,677'Lateral power MOSFET with high breakdown voltage and low on-resistance'20117,911,022'Isolation structure in field device'20117,719,064'High voltage CMOS devices'20107,714,414'Method and apparatus for polymer dielectric surface recovery by ion implantation'20107,521,741'Shielding structures for preventing leakages in high voltage MOS devices'20097,521,342'Semiconductor structure with high-voltage sustaining capability and fabrication method of the same'20097,482,662'High voltage semiconductor device utilizing a deep trench structure'20097,476,591'Lateral power MOSFET with high breakdown voltage and low on-resistance'20097,384,836'Integrated circuit transistor insulating region fabrication method'20087,372,104'High voltage CMOS devices'20087,279,767'Semiconductor structure with high-voltage sustaining capability and fabrication method of the same'20077,221,021'Method of forming high voltage devices with retrograde well'20077,129,559'High voltage semiconductor device utilizing a deep trench structure'20067,122,876'Isolation-region configuration for integrated-circuit transistor'20067,079,412'Programmable MOS device formed by stressing polycrystalline silicon'20066,756,294'Method for improving bump reliability for flip chip devices'20046,593,220'Elastomer plating mask sealed wafer level package method'20036,348,371'Method of forming self-aligned twin wells'20026,338,976'Method for forming optoelectronic microelectronic fabrication with attenuated bond pad corrosion'20026,291,306'Method of improving the voltage coefficient of resistance of high polysilicon resistors'20016,100,154'Using LPCVD silicon nitride cap as a barrier to reduce resistance variations from hydrogen intrusion of high-value polysilicon resistor'20005,972,777'Method of forming isolation by nitrogen implant to reduce bird\'s beak'19995,895,257'LOCOS field oxide and field oxide process using silicon nitride spacers'19995,872,042'Method for alignment mark regeneration'19995,866,947'Post tungsten etch bank anneal, to improve aluminum step coverage'19995,858,854'Method for forming high contrast alignment marks'19995,804,488'Method of forming a tungsten silicide capacitor having a high breakdown voltage'19985,757,045'CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation'19985,726,091'Method of reducing bird\'s beak of field oxide using reoxidized nitrided pad oxide layer'19985,705,320'Recovery of alignment marks and laser marks after chemical-mechanical-polishing'19985,702,972'Method of fabricating MOSFET devices'19975,691,212'MOS device structure and integration method'19975,668,024'CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation process'19975,641,710'Post tungsten etch back anneal, to improve aluminum step coverage'19975,597,442'Chemical/mechanical planarization (CMP) endpoint method using measurement of polishing pad temperature'19975,554,558'Method of making high precision w-polycide-to-poly capacitors in digital/analog process'19965,530,418'Method for shielding polysilicon resistors from hydrogen intrusion'19965,510,637'Fabrication of w-polycide-to-poly capacitors with high linearity'19965,480,828'Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process'19965,460,993'Method of making NMOS and PMOS LDD transistors utilizing thinned sidewall spacers'19955,451,529'Method of making a real time ion implantation metal silicide monitor'19955,338,701'Method for fabrication of w-polycide-to-poly capacitors with high linearity'19945,108,937'Method of making a recessed gate MOSFET device structure'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2013Patents assigned to TAIWAN SEMICONDUCTOR MFG (45)· patent assignee history
1992–2009Based in Taipei, TW· patent location history
1994–2013Based in Hsinchu, TW· patent location history
1999Based in Fonghua Village, TW· patent location history
2006–2010Based in Hsin Chu, TW· patent location history
2012–2013Patents assigned to HSU SHUN-LIANG (4)· patent assignee history
2012–2013Patents assigned to LIU RUEY-HSIN (3)· patent assignee history
2012–2013Patents assigned to CHIANG PUO-YU (2)· patent assignee history
2012–2013Patents assigned to HUANG TSUNG-YI (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 45 | 1992–2013 |
| HSU SHUN-LIANGself | 4 | 2012–2013 |
| LIU RUEY-HSIN | 3 | 2012–2013 |
| CHIANG PUO-YU | 2 | 2012–2013 |
| HUANG TSUNG-YI | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 40 | 1994–2013 |
| Taipei, TW | 4 | 1992–2009 |
| Hsin Chu, TW | 3 | 2006–2010 |
| Fonghua Village, TW | 1 | 1999 |