Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance

1. Field of the Invention

This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of silicon on insulator (SOI) devices and more particularly to a method for fabricating complementary silicon on insulator (CSOI) devices that can be partially depleted and fully depleted using wafer bonding and more particularly to a method for forming optional air gaps in insulating regions in silicon on insulator (SOI) devices.

2. Description of the Prior Art

Integrated circuits (ICs) include a multitude of transistors formed on a semiconductor substrate. Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally bulk semiconductor-type devices or silicon-on-insulator (SOI)-type devices.

The removal of portions of the first substrate can comprises a grinding process, an etching process (KOH) or a SMART CUT process; a process comprising a H 2 implant and anneal.

According to conventional complimentary metal oxide semiconductor (CMOS) fabrication techniques, the reduction of the depletion layer thickness is realized by a super-steep retrograded well (SSRW) ion implantation process. However, this process is limited by the diffusion of dopant atoms during subsequent thermal processes (e.g., annealing).

Conventional SOI-type devices include an insulative substrate attached to a thin film semiconductor substrate which contains transistors similar to the MOSFET described with respect to bulk semiconductor-type devices. The transistors have superior performance characteristics due to the thin film nature of the semiconductor substrate and the insulative properties of the insulative substrate. The superior performance is manifested in superior short channel performance (i.e., resistance to process variation in small size transistor), near-ideal subthreshold voltage swing (i.e., good for low off-state current leakage), and high saturation current.

Silicon on insulator (SOI) devices have been dubbed as the next successor to the reigning Complementary Metal On Silicon (CMOS) devices. Silicon on insulator (SOI) has excellent isolation properties. Silicon on insulator (SOI) has existed for almost two decades, but still improved methods for making silicon on insulator (SOI) devices are needed to advance the technology.

The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 4,169,000(Riseman) shows a STI air gap and a wafer bonded thereover. U.S. Pat. No. 6,084,271(Yu et al.) shows a silicon on insulator (SOI) process with wafer bonding and shallow trench isolation (STI). U.S. Pat. No. 5,988,292(Black et al.) teaches a method to join multiple wafer using STI and wafer bonding. U.S. Pat. No. 5,985,728(Jennings) shows a SOI process with wafer bonding and a boron layer. U.S. Pat. No. 6,013,936(Colt, Jr.) teaches a double SOI device. U.S. Pat. No. 5,484,738(Chu et al.) teaches a Bonded SOI device/process.

It is an object of the present invention to provide a method to form a silicon on insulator (SOI) device.

It is an object of the present invention to provide a method to form a silicon on insulator (SOI) device that uses wafer bonding technique.

It is an object of the present invention to provide a method to form a silicon on insulator (SOI) device that uses wafer bonding technique that can be use to form fully and partially depleted complementary devices.

It is another object of the invention to provide a method to form a silicon on insulator device that uses wafer bonding techniques that can be used to make fully and partially depleted complementary devices with optional air gaps in insulating regions.

To accomplish the above objectives, the present invention provides a method of manufacturing a SOI device.

A first substrate is provided having trenches in a first side. The first substrate has a second side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to from isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. The second substrate has a second side. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.

Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.

The features and advantages of a semiconductor device according to the present invention and further details of a process of fabricating such a semiconductor device in accordance with the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:

FIGS. 1, 2 A, 3 , 4 A, and 6 A are cross sectional views for illustrating a first embodiment of the method for manufacturing a SOI device according to the present invention.

FIGS. 1, 2 B, 3 , 4 B, 5 and 6 B are cross sectional views for illustrating a second embodiment of the method for manufacturing a SOI device according to the present invention.

FIGS. 1, 2 C, 3 , 4 C, and 6 C are cross sectional views for illustrating a third embodiment of the method for manufacturing a SOI device according to the present invention.

The present invention will be described in detail with reference to the accompanying drawings. The present invention provides a method of forming a

The invention had three preferred embodiments. The three embodiment differ in the amount of oxide 20 that is removed (see FIGS. 2A, 2 b , and 2 C).

The first embodiment is shown in FIG. 6 A. The first embodiment forms a SOI device without air gaps and without a buried oxide layer.

The second embodiment forms a SOI device with air gaps. See FIG. 6 B. The second embodiment is similar to the first embodiment, but forms a gap 16 between the first substrate 10 and the insulating layer 210 . See FIGS. 2B and 4B. The second embodiment etches back the first substrate 10 after the STI regions 20 B are formed. See FIG. 2 b.

The third embodiment (See FIG. 6C) forms a SOI device with a buried oxide layer 20 C between the active area 10 C and the oxide layer 210 .

A. First Embodiment

The final result of the first embodiment is shown in FIG. 6 A.

FIGS. 1, 2 A, 3 , 4 A, and 6 A are cross sectional views for illustrating a first embodiment of the method a for manufacturing a SOI device according to the present invention.

As shown in FIG. 1, a first substrate 10 is provided having trenches 18 in a first side 11 . The first substrate 10 have a second side 12 .

The first substrate 10 is preferably comprised of monocrystalline silicon. The first substrate 10 is preferably comprised of monocrystalline silicon with a p-type doping of approximately 1E16 atom/cc. However, a substrate (e.g., wafer) with a different doping concentration and/or N-type doping could be used, depending on the final device requirements.

The trenches 18 preferably have a top width 18 B between 0.35 μm and greater than 10 μm. and more preferably between 0.35 μm and 10 μm. The trenches 18 preferably have a bottom width 18 A between 0.30 and greater than 10 μm and more preferably between 0.3 μm and 10 μm (depending on the low-out & depth of trench). The trenches 18 preferably have a depth 18 C between 800 and 3000 Å.

The first substrate (e.g., active area) between the top of the trenches 18 preferably has a width 22 B between 0.50 and 100 μm and the first substrate between the bottom of the trenches has a width 22 A between 0.6 μm and 100 μm.

Still referring to FIG. 1, we form a first insulating layer 20 over the first side 11 of the first substrate and filling the trenches 18 . The first insulating layer is preferably comprised of oxide and has a thickness of between about 800 (for fully depleted SOI) and 3000 (for partially depleted SOI) Å (after planarization).

As shown in FIG. 2A, the first insulating layer 20 is planarized to expose the first side 11 of the first substrate 10 to form isolation regions (e.g., STI) 20 A.

As shown in FIG. 3, we provide a second substrate 200 having a second insulating layer 210 over a first side 201 of the second substrate. The second substrate has a second side 202 . The second substrate is composed of Si similarly to the first substrate.

The second insulating layer 210 is comprised of oxide and has a thickness of between about 1000 and 10,000 Å. The second substrate is comprised of monocrystalline silicon and has a thickness of between about 500 and 700 μm.

As shown in FIG. 4A, we bond the second insulating layer 210 to the first insulating layer 20 A.

Next, we thin the first substrate from the second side 12 . We remove portions of the first substrate 10 from the second side 12 to expose the first insulating layer 20 to form active areas 10 a between the isolation regions 20 A.

The removal of portions of the first substrate can comprises a grinding process, an etching process (KOH) or a SMART CUT process; a process comprising a H 2 implant and anneal. A SMART CUT process preferably comprises implanting H 2 into a wafer and annealing the wafer at about greater than 1000° C. The wafer will break into two at the implant depth/level.

Next, we preferably thermally anneal the active areas 10 A thereby removing defects in the active areas 10 A. The thermal anneal is preferably performed at a temperature between 1200 and 1400° C. for a time between 10 and 30 minutes.

As shown in FIG. 6A, devices can be fabricated in these regions using conventional process steps dictated by the type or types of devices desired. As shown in FIG. 6 a , we form devices in and on the active areas 10 a . In addition, the active areas can be doped to form N-well and or p-well so that NMOS and PMOS (or PFET and NFET) devices. Obviously, other devices can be formed in and on the active regions, such as resistors and capacitors.

B. Second Embodiment

The second embodiment is similar to the first embodiment, but forms a gap 16 between the first substrate 10 and the insulating layer 210 . See FIGS. 2B and 4B. The second embodiment etches back the first substrate 10 after the STI regions 20 B are formed. See FIG. 2 b . The description above for the first embodiment applies to the second and third embodiments with the exception of the formation of the gap 16 .

The final result of the second embodiment is shown in FIG. 6 b . FIGS. 1, 2 B, 3 , 4 B, 5 and 6 B are cross sectional views for illustrating a second embodiment of the method a for manufacturing a SOI device according to the present invention.

As shown in FIG. 1, a first substrate 10 is provided having trenches 18 in a first side 11 . The first substrate 10 has a second side 12 .

The first substrate 10 is preferably comprised of monocrystalline silicon. The first substrate 10 is preferably comprised of monocrystalline silicon with a p-type doping of approximately 1E16 atom/cc. However, a substrate (e.g., wafer) with a different doping concentration and/or N-type doping could be used, depending on the final device requirements.

The trenches 18 preferably have a top width 18 B between 0.35 and greater than 10 μm and more preferably between 0.35 and 10 μm; and a bottom width 18 A between 0.3 and than 10 μm and more preferably between 0.30 and 10 μm. The trenches 18 preferably have a depth 18 C between 800 and 3000 Å.

The first substrate between the top of the trenches having a width 22 B between 0.35 and 100 μm and more preferably between 0.35 and 10 μm; and the first substrate between the bottom of the trenches having a width 22 A between 0.6 μm and 100 μm and more preferably between 0.6 and 10 μm.

Still referring to FIG. 1, we form a first insulating layer 20 over the first side 11 of the first substrate and filling the trenches 18 . The first insulating layer is preferably comprised of oxide and has a thickness of between about 800 (for fully depleted SOI (˜no body Si) devices and 3000 Å (for partially depleted SOI) after planarization.

As shown in FIG. 2B, the first insulating layer 20 is planarized to expose the first side 11 of the first substrate 10 to form isolation regions (e.g., STI) 20 b.

As shown in FIG. 2 b , in a critical step, we remove portions of the first side 10 of the first substrate 10 to form recesses 14 between the isolation regions (e.g., STI) 20 b . This is a major difference between the second embodiment and the first embodiments.

The recesses 14 preferably have a depth 15 between about 200 and 1500 Å. This is intended to ensure total isolation so that there is no conduction across the oxide.

As shown in FIG. 3, we provide a second substrate 200 having a second insulating layer 210 over a first side 201 of the second substrate. The second substrate has a second side 202 . The second substrate is composed of Si similarly to the first substrate.

As shown in FIG. 4B, we bond the second insulating layer 210 to the first insulating layer 20 A to form (air) gaps 16 between the second insulating layer 210 and the first substrate 10 B.

As shown in FIG. 5B, we thin the first substrate 10 from the second side 12 . We remove portions of the first substrate 10 from the second side 12 to expose the first insulating layer 20 to form active areas 10 b between the isolation regions 20 b.

The removal of portions of the first substrate can be performed by a grinding process, an etching process (KOH) or a SMART CUT process; a process comprising a H 2 implant and anneal.

Next, we thermally anneal the active areas 10 A thereby removing defects in the active areas 10 A. The thermal anneal is preferably performed at a temperature between 1200° C. and 1400° C. for a time between 10 and 30 minutes.

As shown in FIG. 6B, devices can be fabricated in these regions using conventional process steps dictated by the type or types of devices desired. As shown in FIG. 6 b , we form devices in and on the active areas 10 b . In addition, the active areas can be doped to form N-well and or p-well so that NMOS and PMOS (or PFET and NFET) devices. Obviously, other devices can be formed in and on the active regions, such as resistors and capacitors.

C. Third Embodiment

The third embodiment is similar to the first embodiment, but leaves a thickness of the insulating layer 20 C between the active area 10 C and the insulating layer 210 . See FIG. 6 C. In a critical step shown in FIG. 2C, the second embodiment planarizes the back the insulating layer 20 C to not expose the first substrate 10 . The description above for the first embodiment applies to the second and third embodiments with the exception of the formation of the gap 16 .

The final result of the third embodiment is shown in FIG. 6 c . FIGS. 1, 2 C, 3 , 4 C, and 6 C are cross sectional views for illustrating a third embodiment of the method a for manufacturing a SOI device according to the present invention.

As shown in FIG. 1, a first substrate 10 is provided having trenches 18 in a first side 11 . The first substrate 10 have a second side 12 .

The first substrate 10 is preferably comprised of monocrystalline silicon. The first substrate 10 is preferably comprised of monocrystalline silicon with a p-type doping of approximately 1E16 atom/cc. However, a substrate (e.g., wafer) with a different doping concentration and/or N-type doping could be used, depending on the final device requirements.

The trenches 18 preferably have a top width 18 B between 0.35 μm and greater than 10 μm. and more preferably between 0.35 μm and 10 μm; and a bottom width 18 A between 0.60 and greater than 10 μm and more preferably between 0.6 μm and 10 μm. The trenches 18 preferably had depth 18 C between 800 and 3000 Å.

The first substrate between the top of the trenches having a width 22 B between 50 and 100 μm and the first substrate between the bottom of the trenches having a width 22 A between 0.6 μm and 100 μm.

Still referring to FIG. 1, we form a first insulating layer 20 over the first side 11 of the first substrate and filling the trenches 18 . The first insulating layer is preferably comprised of oxide and has a thickness of between about 800 (fully depleted SOI) and 3000 (partially depleted SOI) Å.

As shown in FIG. 2C, the first insulating layer 20 C is planarized to not to expose the first side 11 of the first substrate 10 to form isolation regions (e.g., STI) 20 c . The first insulating layer 20 C preferably has a thickness 22 of between about 1000 and 3000 Å over the substrate 10 C (after planarization).

As shown in FIG. 3, we provide a second substrate 200 having a second insulating layer 210 over a first side 201 of the second substrate. The second substrate has a second side 202 . The second substrate is composed of Si similarly to the first substrate.

The second insulating layer 210 is comprised of oxide and has a thickness of between about 1000 and 7000 Å. The second substrate is comprised of monocrystalline silicon and has a thickness of between about 500 and 700 μm.

As shown in FIG. 4C, we bond the second insulating layer 210 to the first insulating layer 20 c to form gaps 16 between the second insulating layer 210 and the first substrate 10 c.

A shown in FIG. 6 c , we thin the first substrate 10 from the second side 12 . We removing portions of the first substrate 10 C from the second side 12 to expose the first insulating layer 20 C to form active areas 10 C between the isolation regions 20 c;

The removal of portions of the first substrate can comprises a grinding process, an etching process (KOH) or a smart cut process.

Next, we thermally anneal the active areas 10 A thereby removing defects in the active areas 10 A. The thermal anneal is preferably performed at a temperature between 1200 and 1400° C. for a time between 10 and 30 minutes.

As shown in FIG. 6 c , devices can be fabricated in these regions using conventional process steps dictated by the type or types of devices desired. As shown in FIG. 6 c , we form devices in and on the active areas 10 c . In addition, the active areas can be doped to form N-well and or p-well so that NMOS and PMOS (or PFET and NFET) devices. Obviously, other devices can be formed in and on the active regions, such as resistors and capacitors.

Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word about or approximately preceded the value of the value or range.

In the above description numerous specific details are set forth such as flow rates, pressure settings, thicknesses, etc., in order to provide a more thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these details. In other instances, well known process have not been described in detail in order to not unnecessarily obscure the present invention. Also, the flow rates in the specification can be scaled up or down keeping the same molar % or ratios to accommodate difference sized reactors as is known to those skilled in the art.

Although this invention has been described relative to specific insulating materials, conductive materials and apparatuses for depositing and etching these materials, it is not limited to the specific materials or apparatuses but only to their specific characteristics, such as conformal and non-conformal, and capabilities, such as depositing and etching, and other materials and apparatus can be substituted as is well understood by those skilled in the microelectronics arts after appreciating the present invention

While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. It is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.