Inventor

Alex See

Inventor

Singapore, SG

Overview

2000–2017

Patent span

Electricity

Primary field (CPC H)

Patents· 54 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1029%

H10DInorganic electric semiconductor devices28%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%

H01LSemiconductor devices6%

H10BElectronic memory devices3%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

B24BMachines, devices, or processes for grinding or polishing2%

C08JWorking-up1%

C11DDetergent compositions1%

G01BMeasuring length, thickness or similar linear dimensions1%

PatentTitleYear

9,627,219'CMP wafer edge control of dielectric'2017 9,349,654'Isolation for embedded devices'2016 9,287,197'Through silicon vias'2016 9,242,338'CMP head structure'2016 9,242,341'CMP head structure'2016 9,230,886'Method for forming through silicon via with wafer backside protection'2016 9,034,720'Litho scanner alignment signal improvement'2015 9,023,725'Filament free silicide formation'2015 8,940,637'Method for forming through silicon via with wafer backside protection'2015 8,852,968'STI CMP under polish monitoring'2014 8,836,139'CD control'2014 8,828,858'Spacer profile engineering using films with continuously increased etch rate from inner to outer surface'2014 8,569,173'Methods of protecting elevated polysilicon structures during etching processes'2013 8,518,775'Integration of eNVM, RMG, and HKMG modules'2013 8,492,236'Step-like spacer profile'2013 8,415,236'Methods for reducing loading effects during film formation'2013 8,354,347'Method of forming high-k dielectric stop layer for contact hole opening'2013 7,112,499'Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal'2006 7,030,451'Method and apparatus for performing nickel salicidation'2006 6,905,964'Method of fabricating self-aligned metal barriers by atomic layer deposition on the copper layer'2005 6,899,857'Method for forming a region of low dielectric constant nanoporous material using a microemulsion technique'2005 6,897,118'Method of multiple pulse laser annealing to activate ultra-shallow junctions'2005 6,890,854'Method and apparatus for performing nickel salicidation'2005 6,878,623'Technique to achieve thick silicide film for ultra-shallow junctions'2005 6,780,691'Method to fabricate elevated source/drain transistor with large area for silicidation'2004 6,777,329'Method to form C54 TiSi2 for IC device fabrication'2004 6,764,914'Method of forming a high K metallic dielectric layer'2004 6,734,072'Method of fabricating a MOSFET device using a spike rapid thermal oxidation procedure'2004 6,727,151'Method to fabricate elevated source/drain structures in MOS transistors'2004 6,680,239'Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant'2004 6,638,365'Method for obtaining clean silicon surfaces for semiconductor manufacturing'2003 6,630,405'Method of gate patterning for sub-0.1 m technology'2003 6,624,489'Formation of silicided shallow junctions using implant through metal technology and laser annealing process'2003 6,613,652'Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance'2003 6,602,801'Method for forming a region of low dielectric constant nanoporous material'2003 6,492,242'Method of forming of high K metallic dielectric layer'2002 6,475,875'Shallow trench isolation elevation uniformity via insertion of a polysilicon etch layer'2002 6,472,697'Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application'2002 6,468,880'Method for fabricating complementary silicon on insulator devices using wafer bonding'2002 6,436,833'Method for pre-STI-CMP planarization using poly-si thermal oxidation'2002 6,432,797'Simplified method to reduce or eliminate STI oxide divots'2002 6,399,471'Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application'2002 6,391,731'Activating source and drain junctions and extensions using a single laser anneal'2002 6,387,747'Method to fabricate RF inductors with minimum area'2002 6,380,066'Methods for eliminating metal corrosion by FSG'2002 6,365,446'Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process'2002 6,355,563'Versatile copper-wiring layout design with low-k dielectric integration'2002 6,348,385'Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant'2002 6,335,253'Method to form MOS transistors with shallow junctions using laser annealing'2002 6,319,767'Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique'2001 6,303,418'Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer'2001 6,281,082'Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill'2001 6,261,935'Method of forming contact to polysilicon gate for MOS devices'2001 6,103,594'Method to form shallow trench isolations'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2006Patents assigned to CHARTERED SEMICONDUCTOR MFG (36)· patent assignee history

2000–2017Based in Singapore, SG· patent location history

2003Based in Woodlands, SG· patent location history

2013–2017Patents assigned to GLOBALFOUNDRIES SG PTE LTD (17)· patent assignee history

2013–2015Patents assigned to LIU HUANG (6)· patent assignee history

2013–2015Patents assigned to ZOU ZHENG (6)· patent assignee history

2013–2015Patents assigned to CONG HAI (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
CHARTERED SEMICONDUCTOR MFG	36	2000–2006
GLOBALFOUNDRIES SG PTE LTD	17	2013–2017
LIU HUANG	6	2013–2015
ZOU ZHENG	6	2013–2015
CONG HAI	4	2013–2015

Locations

Location	Patents	Span
Singapore, SG	53	2000–2017
Woodlands, SG	1	2003