On-line cancellation of sampling mismatch in interleaved sample-and-hold circuits

The present invention relates generally to electrical circuits, and more particularly to a system and method for reducing sampling mismatch in sample and hold circuits.

Analog to digital converters (ADCS) are important analog circuit devices which take an analog input signal and generate one or more digital signals which are representative of the analog input. ADCs are used in many applications such as communications applications in which the components receive a voice input (an analog input) and transform the voice date into a digital format for internal processing. Exemplary applications using such ADCs are illustrated in prior art FIGS. 1 and 2, respectively. For example, in prior art FIG. 1, an exemplary base transceiver station (BTS) 10 is illustrated in which an RF analog input signal 12 is received, amplified and converted into a digital signal 14 before being processed in a baseband section 16 and network interface section 18 . Similarly, prior art FIG. 2 illustrates a schematic diagram of an automobile multimedia system 20 in which various analog signals such as radio signals 22 and sensor signals 24 are transformed into digital signals for subsequent processing. Further, many other system applications exist, including, but not limited to, data communication receivers or hard disk drive (HDD) read channel applications such as the system 26 of prior art FIG. 3 .

One of the most challenging portions of an ADC is the sample and hold (S/H) circuit at the front end thereof. As the speed of ADCs continues to grow, the design of the S/H circuit becomes more challenging, and various solutions have been proposed to improve the speed of such S/H circuits. One prior art circuit solution for improving the speed of a S/H circuit is illustrated in prior art FIG. 4 and designated at reference numeral 30 . The S/H circuit 30 consists of four S/H subcircuits 32 a - 32 d coupled together in parallel. Each of the S/H subcircuits 32 a - 32 d operates individually as a S/H circuit, wherein the input V IN is passed to the output V OUT during a “sampling mode” and the state of the input is maintained on the output in the “hold mode”, respectively.

The speed of the S/H circuit 30 of FIG. 4 is increased by using several individual S/H subcircuits 32 a - 32 d interleaved in time. An exemplary sample timing diagram for the S/H circuit 30 is illustrated in prior art FIG. 5 . Note that with multiple S/H subcircuits interleaved in time, each subcircuit transitions through one sample and hold cycle during four clock (CLK) cycles, whereas if a similar speed were desired with only a single S/H subcircuit, the sample and hold functions each would have to be completed within a one-half (½) clock cycle. Therefore in the above parallel interleaved configuration, the overall speed is increased without requiring higher performance from the individual S/H subcircuit elements.

Referring again to prior art FIG. 4, although the pass gates at the output of the overall S/H circuit 30 might seem like a possible speed limitation, usually such S/H circuits are followed by one or more output buffers. In such a case, the RC filter of the pass gate and the input capacitance of the output buffer is usually fairly small compared with the speed gained through parallelism.

One problem with the technique provided by the circuit 30 of prior art FIG. 4 is that if the S/H subcircuits 32 a - 32 d are not perfectly matched, then errors can occur. The three chief types of mismatch associated with the interleaved S/H circuit 30 are offset mismatch, gain mismatch and sampling mismatch (which is sometimes referred to as timing mismatch). A brief discussion of the operation of an individual conventional S/H subcircuit is provided below in order to appreciate the impact that sampling mismatch has on the performance of the S/H circuits 30 .

An exemplary prior art sample and hold subcircuit is illustrated in prior art FIG. 6, and designated at reference numeral 40 . Circuit 40 is an exemplary detailed circuit of the structure 32 a in FIG. 4 . Transistor M 1 operates as a sampling switch, and C HOLD acts as a sampling capacitor. In the sampling mode, a sampling signal “S” is asserted, thereby closing a switch 42 , which activates M 1 (turns M 1 on). With M 1 on, V IN is passed to the output V OUT .

A significant time point relating to sampling mismatch in S/H circuits deals with the instant when the sampling switch M 1 is deactivated, or turned off. Any deviation of the deactivation of M 1 from perfect CLK/N time periods will cause a sampling mismatch between the various subcircuits (e.g., 32 a - 32 d ) and result in distortion at the output V OUT (e.g., resulting in undesired “tones” at the output at f in ±f s /N, wherein f in is the frequency of V IN , f s is the sampling frequency, and N represents the number of interleaved channels). To deactivate M 1 , the sample signal “S” goes low (opening switch 42 ) and a hold signal “H” is asserted, which causes a switch 43 to close. This instance pulls the gate of M 1 down to ground, thus turning M 1 off. Each S/H subcircuit has its own hold signal “H”; consequently, a primary source of the sampling mismatch relates to mismatches in the switch M 1 driven by “H” and the arrival of the hold signal “H” at each subcircuit switch, respectively. In addition, even if no sampling mismatch occurs between the hold signals (“H”) of the various subcircuits 32 a - 32 d, a sizing mismatch of switch 43 or M 1 between the various subcircuits may exist which may contribute disadvantageously to sampling mismatch.

There is a need in the art for a circuit and method for increasing the speed in sample and hold circuits in which timing mismatch is reduced substantially.

According to the present invention, a system and method of reducing sampling mismatch in high speed S/H circuits is disclosed.

According to the present invention, sampling mismatch, for example, related to the sampling switch in various S/H subcircuits, is reduced by calibrating the subcircuits, for example, by modifying a delay associated with the hold signal of the subcircuits so as to minimize sampling mismatch between S/H subcircuits. In the above manner, the sampling mismatch between the various S/H subcircuits associated with the arrival of the hold signal at its switch in each subcircuit is reduced substantially or eliminated altogether.

The present invention is directed to a system and method for reducing sampling mismatch in high speed S/H circuits. In S/H circuits employing a plurality of time interleaved S/H subcircuits, sampling mismatch is reduced via calibration by modification of the hold signal to thereby establish a predetermined timing relationship between each of the S/H subcircuits. Such calibration is performed “on line”, thereby allowing for calibration of the S/H circuit without disconnecting the circuit chip from the signal path associated therewith in accordance with conventional “off line” calibration techniques.

According to one exemplary aspect of the present invention, calibration among a plurality of time-interleaved S/H subcircuits is accomplished by calibrating each S/H subcircuit separately with a pre-calibrated S/H subcircuit on-chip which serves as a calibration standard. Each calibration with the pre-calibrated S/H subcircuit provides an output result which is analyzed to identify sampling mismatch between the S/H subcircuit under test and the calibration standard. Such analysis is then used to modify the hold signal associated with the S/H subcircuit under test to minimize the timing mismatch.

Therefore the present invention provides for an “on line” calibration system and methodology as opposed to an “off line” type calibration. In order to fully appreciate several of the advantageous features of the present invention, a brief discussion follows below on how an “off line” calibration system operates. A detailed description of the “on line” calibration system and method of the present invention will then follow thereafter.

To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed and the present invention is intended to include all such embodiments and their equivalents. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.

FIG. 1 is a block system level diagram illustrating a prior art base transceiver station utilizing a plurality of ADCs;

FIG. 2 is a block system level diagram illustrating a prior art multimedia controller for an automobile employing a plurality of ADCs;

FIG. 3 is a block system level diagram illustrating a prior art data communication receiver or a disk drive read channel employing an ADC;

FIG. 4 is a simplified schematic diagram illustrating a prior art high speed sample and hold (S/H) circuit having four S/H subcircuits coupled together in parallel, time-interleaved fashion;

FIG. 5 is a timing diagram illustrating an exemplary timing operation for the four S/H subcircuits of prior art FIG. 4;

FIG. 6 is a shematic diagram illustrating an exemplary prior art S/H subcircuit used in prior art FIG. 4 used to help illustrate the problem associated with sampling mismatch in prior art high speed S/H circuits;

FIG. 7 is a combined block and schematic diagram illustrating an off-line calibration system for reducing sampling mismatch in parallel, time-interleaved sample and hold circuits;

FIG. 8 is a combined block and schematic diagram illustrating an on-line calibration system for reducing sampling mismatch in parallel, time-interleaved sample and hold circuit according to the present invention;

FIG. 9 is a series of timing diagrams illustrating a gating function by which clock signals having one frequency may be divided down to a second, lower frequency according to the present invention;

FIG. 10 is a series of timing diagrams illustrating various types of mismatch, namely, gain mismatch, offset mismatch and sampling mismatch, in order to illustrate how sampling mismatch is distilled from other forms of mismatch according to the present invention;

FIG. 11 is a schematic diagram illustrating an exemplary slope detection circuit according to the present invention;

FIG. 12 is a flow chart diagram illustrating a method of reducing sampling mismatch in parallel, time-interleaved sample and hold circuits according to the present invention; and

FIG. 13 is a flow chart diagram illustrating a method of comparing data from one channel of a parallel, time-interleaved sample and hold circuit with calibration data according to the present invention.

The present invention will now be described with respect to the accompanying drawings in which like numbered elements represent like parts.

The present invention is directed to a system and method for reducing sampling mismatch in high speed S/H circuits. In S/H circuits employing a plurality of time interleaved S/H subcircuits, sampling mismatch is reduced via calibration by modification of the hold signal to thereby establish a predetermined timing relationship between each of the S/H subcircuits. Such calibration is performed “on line”, thereby allowing for calibration of the S/H circuit without disconnecting the circuit chip from the signal path associated therewith in accordance with conventional “off line” calibration techniques.

According to one exemplary aspect of the present invention, calibration among a plurality of time-interleaved S/H subcircuits is accomplished by calibrating each S/H subcircuit separately with a pre-calibrated S/H subcircuit on-chip which serves as a calibration standard. Each calibration with the pre-calibrated S/H subcircuit provides an output result which is analyzed to identify sampling mismatch between the S/H subcircuit under test and the calibration standard. Such analysis is then used to modify the hold signal associated with the S/H subcircuit under test to minimize the timing mismatch.

Therefore the present invention provides for an “on line” calibration system and methodology as opposed to an “off line” type calibration. In order to fully appreciate several of the advantageous features of the present invention, a brief discussion follows below on how an “off line” calibration system operates. A detailed description of the “on line” calibration system and method of the present invention will then follow thereafter.

Turning now to the figures, FIG. 7 is a schematic diagram illustrating one exemplary type of “off line” system or circuit for identifying and reducing sampling mismatch in a high speed, parallel coupled S/H circuit, and is designated at reference numeral 100 . The S/H circuit 100 includes a plurality of S/H subcircuits 102 a and 102 b, which are coupled between an input portion 104 (which includes an analog input terminal V IN ) and analog-to-digital converters (ADC 1 106 and ADC 2 108 ), respectively. Each ADC is coupled to a signal analysis circuit 110 , for example, a comparator, which feeds a delay control circuit 112 . Based on the input from the signal analysis circuit 110 , the delay control circuit 112 provides delay control signals 114 and 116 to programmable delay elements 118 and 120 , respectively, which operates to modify a delay associated with the clock signals CLK 1 and CLK 2 .

In operation, the integrated circuit chip employing the system 100 of FIG. 7 receives a suitable calibration signal (V CAL ) to the input portion 104 via a switching network 122 . Based on the delay associated with the programmable delay elements 118 and 120 , modified clock signals 124 and 126 are employed to set the timing for the S/H subcircuits 102 a and 102 b, respectively. The variation in the timing of the clock signals is then apparent in the outputs of the ADCs 106 and 108 . By comparing such outputs via the signal analysis circuit 110 , sampling mismatch associated with the modified clock signals 124 and 126 may be ascertained. The signal analysis circuit 110 then outputs a signal associated with such sampling mismatch to the delay control circuit which uses one or more of the delay control signals 114 and 116 to alter the delays of the programmable delay elements 118 and 120 . The process continues until the sampling mismatch associated with the S/H subcircuits 102 a and 102 b are within an acceptable level.

The above solution works modestly well in calibrating the S/H subcircuits so as to minimize sampling mismatch therebetween. Unfortunately, the S/H subcircuits 102 a and 102 b in FIG. 7 are disconnected from the signal path during such calibration, thus making the calibration occur “off line.” The inventors of the present invention appreciated that by providing a solution in which the S/H subcircuits do not have to be disconnected from the signal path, such calibration may occur “on line” and thus provide minimized sampling mismatch without adversely impacting system performance.

Turning now to FIG. 8, an on-line calibration circuit for calibrating a plurality of S/H subcircuits together is illustrated and designated at reference numeral 200 . The system 200 is similar in some respects to the system 100 of FIG. 7, however, system 200 differs in several ways. Initially, the system 200 of the present invention includes a calibrated S/H subcircuit 202 (S/H(CAL)) and an ADC 204 (ADC(CAL)) which feed the signal analysis circuit 110 . The calibrated S/H subcircuit 202 is fed by a switching arrangement 206 in which CLK 1 or CLK 2 is provided thereto. For example, when the S/H 1 subcircuit 102 a is to be calibrated, CLK 1 is fed to the calibration S/H subcircuit 202 by closing a switch 208 and opening another switch 210 ; likewise opening the switch 208 and closing the switch 210 allows for CLK 2 to be fed to the calibration S/H circuit 202 when S/H 2 circuit 102 b is to be calibrated. Note that although the system 200 of FIG. 8 illustrates only two time interleaved S/H circuits 102 a and 102 b, the present invention contemplates use of a plurality of S/H circuits coupled in parallel generally (e.g., four or more interleaved channels) and such variations are contemplated as falling within the scope of the present invention.

The calibration S/H circuit 202 is initially calibrated offline and its delays are adjusted via delay elements 212 and 214 , respectively, to provide a predetermined timing for the clock signals CLK 1 and CLK 2 , respectively. In addition, an optional gate circuit 216 may be interposed between the switching arrangement 206 and the calibration S/H subcircuit 202 , to divide down the timing signal CLK REF (e.g., either CLK 1 or CLK 2 based on the states of the switches 208 and 210 ) if it is desired to make the calibration S/H subcircuit 202 and its ADC 204 operate at a lower sampling rate. For example, as illustrated in FIG. 9, since the sampling clock for the calibration S/H subcircuit 202 may be either CLK 1 or CLK 2 , the gate circuit 216 may be used to slow down the sampling clock as shown (e.g., divide by 4). Of course, if the gate circuit 216 is not present, then CLK REF is either CLK 1 or CLK 2 depending on which S/H subcircuit is being calibrated.

Returning to FIG. 8, the system 200 further includes a slope detector circuit 220 coupled between the system input and the signal analysis circuit 110 . Since signal distortion at the signal analysis circuit 110 may be due to mismatches other than sampling mismatch (e.g., distortion may be due to gain mismatch and/or offset mismatch), the slope detector circuit 220 operates to distill sampling mismatch from gain and/or offset mismatch in order to generate calibration compensation that focuses primarily on the sampling mismatch (gain mismatch and offset mismatch issues are often addressed separately using other type techniques).

The manner in which the slope detector circuit 220 operates to distill sampling mismatch from other forms of mismatch may be further appreciated in FIG. 10, which illustrates three examples of sample data from ADC 1 106 and ADC(CAL) 204 . In a first example 240 , a gain mismatch is observed in which the peak-to-peak signal amplitude associated with ADC 1 106 is greater than that of ADC(CAL) 204 . In a second example 242 , an offset mismatch is observed, wherein the peak-to-peak signal amplitudes are approximately the same, but offset from one another. Lastly, in a third example 244 , a sampling mismatch is observed, wherein one set of sampling data is out of phase with the other. Note that in the case of sampling mismatch, a unique condition results: when the signal slope is positive, the output of ADC(CAL) 204 is always less than that of ADC 1 106 , and when the signal slope is negative, the output of ADC(CAL) 204 is always greater than ADC 1 106 . This information is then used to generate a unique error signal, for example, as follows:

e phase =sign[slope]×[output of ADC 1 −output of ADC (CAL)]

By accumulating this error over a substantial time interval, errors due to gain mismatch and offset mismatch tend to cancel and thus the sampling mismatch information is distilled therefrom. Thus e phase represents an amount of error due primarily to sampling mismatch and the slope detector circuit 220 may be used to generate such a signal. Using such data, the signal analysis circuit 110 may provide a more accurate analysis.

Various types of slope detector circuits may be utilized and are contemplated as falling within the scope of the present invention. For example, in FIG. 11 a slope detector circuit is illustrated and designated at reference numeral 250 . The analog input signal V IN is sampled at two separate time intervals using a clock signal (e.g., CLK 1 ) and a delayed clock signal (CLK 1 DELAY ), thereby sampling the input signal at two relatively close time intervals across capacitors C 1 and C 2 , respectively, and input to a comparator circuit 252 . When V C1 is greater than V C2 , the comparator 252 outputs a first state (e.g., goes high), thereby signaling a positive slope. Conversely, when V C2 is greater than V C1 , the comparator 252 outputs a second state (e.g., goes low), thereby signaling a negative slope. Other type slope detection circuits, however, may alternatively be used and such alternatives are contemplated as falling within the scope of the present invention. The slope detector circuit 220 is thus operable to generate a digital signal which is indicative of the slope for use in generating an ephase error signal, for example, in the signal analysis circuit 110 .

Returning now to FIG. 8, the on-line calibration system 200 operates in the following exemplary manner. Initially, the calibration S/H subcircuit 202 is calibrated offline using a switching arrangement 260 . For example, one switch 262 is opened which disconnects the analog input (V IN ) from the calibration S/H subcircuit 202 , and another switch 264 is closed which couples a known calibration input signal V CAL thereto. The other switching arrangement 206 is then used to successively couple CLK 1 and CLK 2 to the calibration S/H subcircuit 202 and analyze its output directly or the output of the ADC(CAL) 204 . Using such analysis, the delays associated with delay elements 212 and 214 are configured, respectively, for subsequent calibration of the S/H subcircuits (e.g., 102 a and 102 b ) against the calibration S/H subcircuit 202 .

After the initial calibration, the switch 264 opens and the switch 262 closes, thereby disconnecting V CAL from the calibration S/H subcircuit 202 and coupling the analog input V IN thereto. An on-line calibration phase may then begin between the calibration S/H subcircuit 202 and each of the plurality of S/H subcircuits (e.g., 102 a and 102 b ). Note that although FIG. 8 illustrates only two S/H subcircuits which are time-interleaved, a substantially greater number of such S/H subcircuits may be employed and are contemplated as falling within the scope of the present invention. For example, the on-line calibration of S/H 1 subcircuit 102 a is performed as follows. CLK 1 is coupled to the calibration S/H subcircuit 202 through the delay element 212 and the closed switch 208 , while the switch 210 is open, thereby making a delayed CLK 1 the CLK REF signal that dictates the timing of the calibration S/H subcircuit 202 . Thus the analog input signal V IN is sampled via the calibration S/H subcircuit 202 as dictated by CLK REF . In addition, the S/H 1 subcircuit 102 a also samples the input signal V IN using a delayed version 124 of CLK 1 as dictated by the delay element 118 .

The sampled data, the outputs of ADC 1 106 and ADC(CAL) 204 , are then analyzed or otherwise compared at the signal analysis circuit 110 . Based on such analysis, the signal analysis circuit 110 generates a CLK 1 delay control signal 114 via the delay control circuit 112 which adjusts an amount of delay associated with CLK 1 via the programmable delay element 118 , so as to reduce sampling mismatch between S/H 1 subcircuit 102 a and the calibration S/H subcircuit 202 . In addition, the slope detector 220 also receives the input signal V IN and generates slope information to the signal analysis circuit 110 . The signal analysis circuit 110 then uses the slope information along with the data from the ADCs 106 and 204 to generate an error signal (e.g., e phase ), so that the CLK 1 delay control signal 114 operates to compensate primarily for sampling mismatch as opposed to other signal distortion factors.

Once the S/H 1 subcircuit 102 a is calibrated, the S/H 2 subcircuit 102 b is calibrated in conjunction with the calibration S/H subcircuit 202 in a manner similar to that described above. That is, the outputs of ADC 2 108 and ADC(CAL) 204 are compared along with the slope indication signal taken into account from the slope detector circuit 220 at the signal analysis circuit 110 to generate an error phase signal, which may be used as a CLK 2 delay control signal 116 or generate such a signal. The delay control signal 116 then operates to modify a delay associated with CLK 2 (signal 126 ) via the programmable delay element 120 . By calibrating S/H 1 subcircuits 102 a and 102 b each with respect to the calibration S/H subcircuit 202 , the resulting timing signals 124 and 126 are configured so as to minimize the sampling mismatch therebetween. Furthermore, in doing so, such calibration occurs on-line which allows for calibration to subsequently occur without having to go “offline.” Therefore the present invention allows for an initial offline calibration to occur for the initial calibration S/H subcircuit configuration with all subsequent calibration advantageously occurring online.

According to another aspect of the present invention, a method of performing on-line calibration for time-interleaved sample and hold subcircuits is disclosed, as illustrated in FIG. 12 and designated at reference numeral 300 . While for purposes of simplicity of explanation, the methodology of FIG. 12 is shown and described as a series of steps, it is to be understood and appreciated that the present invention is not limited to the order of steps, as some steps may, in accordance with the present invention, occur in different orders and/or concurrently with other steps from that shown and described herein.

The method 300 begins at step 302 , wherein an offline calibration of the calibration S/H subcircuit is performed. For example, as illustrated in FIG. 8, a plurality of sampling signals (e.g., CLK 1 , CLK 2 ) are modified using delay circuits (e.g., circuits 212 and 214 ). In the above manner, a CLK REF signal is established as a standard by which each of the parallel, time-interleaved S/H subcircuits can be calibrated. Once the offline calibration of the calibration S/H subcircuit is complete, a channel initialization occurs at step 304 .

The slope of the analog input signal (V IN ) is identified at step 306 , for example, by inputting V IN to a slope detection circuit. Alternatively, the slope of the signal may be identified using various forms of signal processing, as may be desired, and any such form of identification is contemplated as falling within the scope of the present invention. The method 300 then continues at step 308 , wherein the data from the Nth channel (e.g., channel 1 when N=1) is compared with the calibration data in an on-line fashion. For example, as illustrated in FIG. 8, with switch 262 closed and switch 264 open, the analog input signal V IN is input to the calibration subcircuit 202 and sampled by ADC(CAL) 204 using the appropriate CLK REF signal. Since channel 1 is being calibrated at this time, CLK REF is a calibrated version of CLK 1 using, for example, closed switch 208 and open switch 210 . The VIN signal is also input to the S/H 1 subcircuit 102 a and ADC 1 106 with CTRL( 208 ) closing the appropriate switch (and CTRL( 210 )) maintaining its switch open) so that the signal analysis circuit 110 compares the data from ADC 1 106 and ADC(CAL) 204 , respectively.

According to the above exemplary aspect of the present invention, the signal analysis comparison of step 308 is performed using digitized data from ADC 1 106 and ADC(CAL) 204 . Alternatively, however, the comparison can be performed using the data directly from the S/H subcircuits (e.g., S/H 1 subcircuit 102 a and subcircuit 202 ), as may be desired. Various forms of signal analysis and/or comparison may be performed to ascertain a degree of sampling mismatch and any such comparison or analysis is contemplated as falling within the scope of the present invention.

For example, turning to FIG. 13, the comparison step 308 may be accomplished by sampling the analog input signal (e.g., V IN ) using the sample signal which has a timing associated with the Nth clock signal (e.g., signal 124 of FIG. 8) to generate Nth channel data at step 310 . Further, the analog input data VIN may be sampled using a sample signal having a timing associated with a pre-calibrated clock signal (e.g., CLK REF ) to generate calibration data at step 312 which may then be compared and/or analyzed using, for example, the signal analysis circuit 110 of FIG. 8 .

The method 300 then further continues at step 310 , wherein a delay control signal is generated for the Nth channel in response to the comparison of step 308 and the slope identified in step 306 . For example, as illustrated in FIG. 8, the signal analysis circuit 110 is operable to generate an e phase signal by which the delay control circuit 112 generates a clock delay control signal (e.g., CLK 1 delay control signal 114 ) to modify a delay associated with a delay element (e.g., delay element 118 ) to vary a timing associated with the clock.

The method 300 then continues at step 316 by determining whether a recalibration is necessary. For example, such a determination may be made by comparing ephase to a predetermined threshold and one ephase is less than the threshold, further calibration is discontinued. Alternatively, however, other analyses may be employed to determine whether further calibration of a given channel is necessary, and such analyses are contemplated as falling within the scope of the present invention. If further calibration is desired (YES at step 316 ), the method 300 returns to step 306 , and steps 306 - 314 are repeated to further reduce sampling mismatch. If no further calibration is deemed necessary (NO at step 316 ), then the next channel is selected by incrementing the variable N, which represents the channel being evaluated for sampling mismatch.

At step 320 , a determination is made whether all the channels in the sample and hold circuit have been calibrated. If not (NO at step 320 ), the method 300 returns to step 306 and steps 306 - 316 are performed for the next channel to reduce sampling mismatch. If all the channels have been calibrated (YES at step 320 ), then the method 300 ends at step 322 . Such an ending may be performed, for example, in FIG. 8 by the opening of switch 262 , however, other discontinuation sequences may be employed and are contemplated as falling within the scope of the present invention.

Although the invention has been shown and described with respect to a certain preferred embodiment or embodiments, it is obvious that equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more other features of the other embodiments as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the term “includes” is used in either the detailed description and the claims, such term is intended to be inclusive in a manner similar to the term “comprising.”