High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus

The present invention relates generally to complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus, and more particularly, relates to a high performance., low cell stress, low power, silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus.

Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. By utilizing SOI technology, designers can increase the speed of digital logic integrated circuits or can reduce their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power.

Various arrangements have been proposed to overcome some of the problems with partially depleted SOI technology. One of the more pronounced problems observed in partially depleted SOI technology is the degraded cell stability. This degraded cell stability is caused by half selected cell disturb sensitivity. With excessive N-channel field effect transistor (NFET) body charge accumulation and uncontrollably low Vt in the access transistor of an SOI RAM cell, the SOI RAM cell content may be unintentionally overwritten under a half-selected condition; that is when it is adjacent to a currently selected cell on the same word line.

A need exists for a high performance, low cell stress, low power, silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus.

A principal object of the present invention is to provide a high performance, low cell stress, low power, silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus. Other important objects of the present invention are to provide such high performance, low cell stress, low power, silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.

In brief, a high performance, low cell stress, low power, silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus are provided. A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sense amplifier includes a precharge circuit for charging complementary data lines to a predefined precharge voltage during a precharge cycle. The precharge voltage is lower than a full rail voltage. A pre-amplifying mechanism produces an offset voltage between the complementary data lines before the sense amplifier is set.

In accordance with features of the invention, the pre-amplifying mechanism includes a pre-amplifying FET that is substantially smaller than a sensing silicon-on-insulator (SOI) FET in the sense amplifier. The full rail voltage is provided for the complementary data lines when the sense amplifier is set. The full rail voltage can be applied during the write mode.

The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:

FIG. 1 is a schematic and block diagram representation illustrating a high performance, low cell stress, silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sense amplifier in accordance with the preferred embodiment;

FIGS. 2A, 2 B, 2 C, 2 D, 2 E, 2 F and 2 G are diagrams with voltage shown with respect to the vertical axis and time shown with respect to the horizontal axis illustrating an exemplary set of control waveforms for the SOI CMOS latch-type sense amplifier of FIG. 1 in accordance with the preferred embodiment; and

FIG. 3 is a diagram with voltage shown with respect to the vertical axis and time shown with respect to the horizontal axis illustrating exemplary complementary data line performance waveforms for the SOI CMOS latch-type sense amplifier of FIG. 1 using the set of control waveforms of FIGS. 2A, 2 B, 2 C, 2 D, 2 E, and 2 F in comparison with a conventional sense amplifier in accordance with the preferred embodiment.

Having reference now to the drawings, in FIG. 1, there is shown a high performance, low cell stress, low power, silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sense amplifier of the preferred embodiment generally designated by the reference character 100 . As shown in FIG. 1, SOI CMOS latch-type sense amplifier 100 includes a pair of P-channel field effect transistors (PFETs) 102 and 104 respectively connected between a voltage supply Vdd and a second pair of cross-coupled P-channel field effect transistors (PFETs) 106 and 108 . PFET 102 is a sense amp preset control PFET. PFET 104 is a sense amplifier triggering PFET that is turned on with gate control sense amp_set_fast_P. A pair of cross-coupled N-channel field effect transistors (NFETs) 110 and 112 are respectively connected to the second pair of P-channel field effect transistors (PFETs) 106 and 108 .

PFET 102 receives a gate input of sense_amp_preset. PFET 104 receives a gate input of sense_amp_set_fast_P. A gate of PFET 106 and NFET 110 is connected to a Data_line_T. A gate of PFET 108 and NFET 112 is connected to a Data_line_C. A pair of NFETs 114 and 116 respectively connected between NFETs 110 and 112 and ground, receives a gate input of sense_amp_set_slow_N and sense_amp_set_fast_N. A pair of P-channel field effect transistors (PFETs) 120 and 122 having a respective gate input of Data_line_T and Data_line_C, are respectively connected between ground and data out, Data_T and Data_C. A gate input of sense_amp_rst is applied to a gate of a plurality of PFETs 124 , 126 and 128 . PFET 124 is connected between voltage Vpch_low and Data_line_T. PFET 128 is connected between voltage Vpch_low and Data_line_C. The voltage Vpch_low is lower than the voltage supply voltage Vdd, and is for example, a mid-rail voltage potential. PFET 126 is connected between Data_line_T and Data_line_C.

A SRAM array 130 are connected by bit lines 132 and bit switches 134 to the data lines, Data_line_T and Data_line_C. Bit lines 132 are referenced as the section of complementary bit lines directly coupled to the RAM cells. Data lines are referenced as the section of complementary bit lines directly coupled to the sense amplifier 100 . Bit lines 132 and data lines, Data_line_T and Data_line_C are separated by bit switches 134 , usually implemented in the form of passgate circuits. The SRAM array 130 includes power rails at voltage supply Vdd and ground. The high voltage of bit lines 132 is voltage supply Vdd or Vpch_low. A circuit block 138 is connected to the data out, Data_T and Data_C of the sense amplifier 100 . The circuit block 138 includes power rails at voltage supply Vdd and ground. Sense amplifier 100 maintains voltage compatibility with other parts of the circuit, such as SRAM ARRAY 130 and circuit block 138 .

In accordance with features of the preferred embodiment, lower than full rail precharge voltage is provided for the complementary bit lines; lower than full rail precharge voltage is provided for the complementary data lines during the precharge cycle; and full rail voltage is provided for the complementary data lines during the sense amplifier firing cycle. Bit lines are biased at a low voltage potential (Vpch_low) as long and as frequently as possible to prevent excessive NFET body charge accumulation and uncontrollably low Vt in the access transistor of an SOI RAM cell. To maintain high sensing sensitivity and performance, data lines are able to operate between Vdd and ground during actual sensing (READ); and bit lines also retain full rail swing between Vdd and ground during WRITE of the cell. Low-current pre-amplifying PFET 102 is activated before triggering and the full amplifying NFETs 110 , 112 and PFETs 106 , 108 are activated after the onset of firing signals.

In accordance with features of the preferred embodiment, sense amplifier 100 operates under a lower-than-full-rail bit line and data line precharge voltage, Vpch_low, while delivering good sensing performance. The bit line voltage is precharged to a level Vpch_low substantially lower than the supply voltage Vdd in order to reduce stress to the memory cell in the form of excessive passgate low-Vt floating body leakage current affecting the storage node, which is the source of half-select instability, that is unintentional WRITE error. To perform a WRITE function, selected bit lines can undergo rail-to-rail operation, as which is most performance beneficial when altering the content of cell needs to be altered during WRITE. Other cells on the same selected word lines still have their bit lines precharged to a voltage lower than full rail such that an unintentional WRITE due to the half select condition can be avoided. Such bit line precharge operation substantially lower than the supply voltage Vdd enhances the reliability of SRAM arrays in a partially depleted SOI technology. Also design characteristics in terms of balancing leakage and performance are optimized.

In accordance with features of the preferred embodiment, the addition of the pre-amplifying PFET 102 in the sense amplifier 100 aids the offset voltage development before the sense amplifier is fired. This effectively compensates the longer transition time needed for the slower side of the data line which goes from mid-rail to the supply voltage Vdd. The sense amplifier 100 maintains high performance in spite of sensing action being initiated from a mid-rail voltage. The “1” side of the data line voltage goes to full Vdd after firing of the sense amplifier 100 and only returns to mid-rail precharged state after passing of data to other parts of the circuit employing normal Vdd. Voltage interface compatibility as well as overall READ performance is thus preserved in this method. Also, the benefit of power saving is achieved as a result of the lower bit line precharge voltage.

Referring to FIGS. 2A, 2 B, 2 C, 2 D, 2 E, 2 F, 2 G and 3 , operation of the sense amplifier 100 may be understood as follows. Pre-amplifying PFET 102 is enabled when the local word lines are turned on. This PFET 102 is made small so that it amplifies the voltage offset in a predictable and linear fashion for a known period of time. When the offset becomes sufficiently mature, the sense amplifier 100 is fired by fully turning on the triggering devices, namely NFET 116 with gate input sense_amp_set_fast_N and PFET 104 with gate input sense_amp_set_fast_P. Both set devices, PFET 104 and NFET 116 are sized to provide adequate current to produce high-gain amplification. PFET 104 and NFET 116 can be triggered at the same time, as shown in FIGS. 2D and 2E, but are not necessarily triggered at the same time. The preamplification action, relying on weak cross-coupled PFET configuration is essential to result in high performance and sense point stability. High performance is achieved by accelerated offset development, as a result of pre-amplification provided by PFET 102 . Sense point stability is achieved via limiting the gain by way of the small preset PFET 102 , which effectively prevents the possibility of current jamming and corruption of the amplifying latch. Because of the effectiveness of preamplification, the need for NFET 114 with gate input sense_amp_set_slow_N usually is eliminated. NFET 114 with gate input sense_amp_set_slow_N is often required in a conventional high performance sense amplifier to bring the precharged lines closer to the sense point.

FIGS. 2A, 2 B, 2 C, 2 D, 2 E, 2 F, 2 G and 3 provide simulations of voltage waveforms to understand the operation of the sense amplifier 100 of the preferred embodiment. It should be understood that the pulse width and alignment should be considered relative depending on specific timing requirement and signal availability. In FIGS. 2A, 2 B, 2 C, 2 D, 2 E, 2 F, 2 G and 3 , the high voltage supply Vdd of sense amplifier 100 is 1.65 Volts. FIG. 2A illustrates a voltage waveform of a local_word_line of SRAM array 130 . FIG. 2B illustrates a voltage waveform of sense_amp_rst applied to the gate of PFETs 124 , 126 and 128 to bias the complementary data lines to Vpch_low. FIG. 2C illustrates a voltage waveform of sense_amp_preset applied to the gate of sense amp preset control PFET 102 . FIGS. 3D and 2E respectively illustrate voltage waveform sense_amp_set_slow_N applied to the gate of sense amp set NFET 114 and voltage waveform sense_amp_set_fast_N applied to the gate of sense amp set NFET 116 . FIG. 2F illustrates a voltage waveform of sense_amp_set_fast_P applied to the gate of sense amp set PFET 104 . FIG. 2G illustrates corresponding voltage waveforms of bit/data_lines. Note the offset voltage developed by the PFET 102 in the voltage waveforms of bit/data_lines.

FIG. 3 illustrates exemplary complementary data line performance waveforms for the SOI CMOS latch-type sense amplifier 100 using the set of control waveforms of FIGS. 2A, 2 B, 2 C, 2 D, 2 E, and 2 F for comparison with a conventional sense amplifier. In FIG. 3, upper curves represent the typical behavior of a conventional high-performance latch-type sense amplifier. Lower curves represent the operation of high-performance latch-type sense amplifier 100 of the preferred embodiment. This comparison is provided with equivalent cross-coupled NFET strength for both amplifier configurations. Both amplifiers are set or fired when at an offset voltage of 150 mV. With the pre-amplification mechanism of the high-performance latch-type sense amplifier 100 of the preferred embodiment, the set signals can be moved earlier by about 200 ps. This not only compensates the slower switching transient due to the larger voltage swing from mid-rail to Vdd, but results in a faster overall sensing speed by over 100 ps. In an optimized design, the beta ratio should favor the slower mid-rail to Vdd transition to improve that part of the slope, δV/δt.

While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.