Inventor
Douglas M. Dewanz
Inventor
Rochester, MN, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%
H01LSemiconductor devices26%
H10DInorganic electric semiconductor devices16%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
G11CStatic stores8%
G06FElectric digital data processing4%
H04LTransmission of digital information, e.g. telegraphic communication2%
PatentTitleYear
9,369,308'Signal transmission reducing coupling caused delay variation'20169,252,100'Multiple-patterned semiconductor device channels'20169,111,935'Multiple-patterned semiconductor device channels'20159,105,639'Semiconductor device channels'20159,099,533'Semiconductor device with distinct multiple-patterned conductive tracks on a same level'20159,099,471'Semiconductor device channels'20159,099,462'Signal path and method of manufacturing a multiple-patterned semiconductor device'20159,093,451'Signal path and method of manufacturing a multiple-patterned semiconductor device'20159,087,879'Method of making semiconductor device with distinct multiple-patterned conductive tracks on a same level'20159,082,624'Signal path of a multiple-patterned semiconductor device'20159,076,848'Semiconductor device channels'20159,070,751'Semiconductor device channels'20159,021,407'Signal path of a multiple-patterned semiconductor device'20158,866,306'Signal path and method of manufacturing a multiple-patterned semiconductor device'20148,809,156'Method for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications'20148,107,309'Bias temperature instability-influenced storage cell'20126,643,804'Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test'20036,404,686'High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus'20026,275,427'Stability test for silicon on insulator SRAM memory cells utilizing disturb operations to stress memory cells under test'20014,849,904'Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989–2016Patents assigned to IBM (20)· patent assignee history
1989–2016Based in Rochester, MN, US· patent location history
2012Patents assigned to DEWANZ DOUGLAS M (1)· patent assignee history
2012Patents assigned to FREIBURGER PETER T (1)· patent assignee history
2012Patents assigned to PAULSEN DAVID P (1)· patent assignee history
2012Patents assigned to SHEETS II JOHN E (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 20 | 1989–2016 |
| DEWANZ DOUGLAS Mself | 1 | 2012 |
| FREIBURGER PETER T | 1 | 2012 |
| PAULSEN DAVID P | 1 | 2012 |
| SHEETS II JOHN E | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Rochester, Minnesota, US | 20 | 1989–2016 |