Integrated high quality diode

The field of the invention is SOI integrated circuit processing to form an integrated circuit including field effect transistors (FETS) and diodes.

Integrated circuits routinely use diodes according to the requirements of the circuit designer. In contemporary sub-micron FET processing, however, it is customary to employ “halo” or “pocket” implants in order to improve short-channel behavior of MOSFETs. This has the side effect of making P-N junctions that receive the halo implant leaky, so that they are not suited for use as band gap voltage regulators and for other requirements of analog circuits.

One could simply add process steps to form a high-quality diode, of course, but that would increase process complexity and therefore increase circuit cost.

It would be advantageous if a high-quality diode could be formed for analog applications that made use of process steps that were already present in a process.

The invention relates to a method of forming a high-quality diode in an SOI process, in which the steps of forming the diode are also used in forming other devices in the circuit, thus providing the diode without adding process complexity.

A feature of the invention is the use of an implant dose made available for the formation of buried precision resistors to form one side of the diode.

Another feature of the invention is the use of FET elements to form the active region of the P-N junction below the gate oxide and away from the source/drain edges used to contact the P-N diode.

Another embodiment of the invention is the use of a blocking insulator, normally used to form active resistor regions, to form and passivate the surface of a P-N diode junction and to block the diode from being shorted during the suicide step.

An advantageous feature of the invention is the use of the buried resistor implant, which is defined by photoresist, so that the P-N junction can be located at a preferred location, rather than using the source/drain implant, which is defined by a polysilicon layer and is not flexible in location.

FIG. 1 shows in cross section a completed diode according to the invention.

FIG. 2 shows in cross section the area of FIG. 1 after the step of forming shallow trench isolation.

FIG. 3 shows in cross section the same area after the implantation of the buried resistor dose.

FIG. 4 shows in cross section the same area after the implantation of the optional p-well.

FIG. 5 shows in cross section the same area after the optional implantation of the N-type source/drain dose.

FIG. 6 shows in cross section the same area after the implantation of the P-type source/drain dose.

FIG. 7 shows the result of an alternative embodiment.

FIG. 8 shows the formation of a shallow trench for isolation.

FIG. 9 shows the use of the P-well implant to dope the active area of the diode.

FIG. 10 shows implantation of the cathode of the diode.

FIG. 11 shows the implantation of the p + area of the diode.

FIG. 12 shows the result of depositing a passivation layer.

Referring now to FIG. 2, there is shown a portion of a silicon on insulator (SOI) integrated circuit that will contain a diode according to the invention. Substrate 10 has a conventional layer of buried insulator (oxide) 26 above it and between p-type silicon device layer 30 .

A pattern of shallow isolation trenches (STI) 25 has been formed to isolate the various devices from one another. Most of the devices will be field effect transistors (FETs), illustratively both NFETs and PFETs. The area 31 between the STI areas 25 , illustratively doped p-, is referred to as the active area in general and as the diode active area when it will contain a diode according to the invention. Illustratively, the dimension extending in the left-right direction in the drawing is the same for the diode and for the FETS, with the length perpendicular to the paper extending as required in order to provide the desired current capacity. The process of forming the STI pattern—etching the trenches, filling them with oxide and chemical-mechanical polishing to remove excess oxide and define a common top surface is conventional, well known to those skilled in the art.

Next, in FIG. 3, a layer of resist 132 has been formed and patterned to define a set of apertures, not shown, that will receive a buried resistor implant, illustratively 2×10 15 /cm 2 of phosphorous at 50 keV. The same dose is implanted in the aperture shown, doping the exposed silicon from its initial doping density of 5×10 15 /cm 3 to a concentration suitable for diode operation and forming the N-doped section of the diode 32 . The magnitude of the dose is not important—one of the advantageous features of the invention being that it provides two functions from several steps, thus saving on process complexity and cost. At the left of the aperture P-N junction 33 is the P-N junction of the diode. It is another advantageous feature of the invention that junction 33 is defined by resist, rather than by the polysilicon of the transistor gate, as is the case for the source/drain implants. The simultaneous use of the resistor-defining resist not only reduces cost, it also permits flexibility in locating the junction. Note that the aperture extends over STI area 25 , providing tolerance in the aperture location. The diode aperture will be referred to in the claims as extending from the first edge of the STI to the diode junction.

Next, in FIG. 4, there is shown an optional step of implanting a dose of p-type ions in a corresponding aperture over the P-N diode. The aperture extends from one STI 25 to the other for ease in alignment. Since this dose is less by three orders of magnitude than the dose in FIG. 3, it has no significant effect on element 32 . The dose is referred to as optional in the event that the initial doping level of the device layer (or in a well in the device layer) is satisfactory. This dose also serves two functions. In the remainder of the circuit, it is the NFET threshold adjust, illustratively 2×10 12 /cm 2 of BF 2 at 25 keV and 4×10 12 /cm 2 boron at 50 keV. The p-type region is denoted by the numeral 36 and the right aperture edge in the figure is denoted by the numeral 33 ′.

Referring now to FIG. 5, there is shown the results of further steps. Gate oxide 42 , gate 44 and gate sidewalls 46 have all been formed simultaneously with the corresponding steps in FET formation. Gate oxide 42 in this case serves as a high-quality, passivated surface for the diode junction. Gate 44 will serve to protect the diode junction during the conventional later step of forming suicide to provide better contacts to the transistors. The optional step being illustrated in FIG. 5 is that of the NFET source/drain implantation defined by resist 134 , which provides an ohmic contact 32 ′ for the diode. This implantation is used in the event that the resistor implantation shown in FIG. 3 is not sufficient to provide for good electrical contact to the silicide to be formed over the cathode. Only one side of the diode is exposed for the implant in this aperture. A corresponding aperture and implant will be formed to provide an ohmic contact 36 on the p-type side as shown in FIG. 6 . This implant is the same implant used in the p-type FET sources and drains, typically 5×10 15 /cm 2 BF 2 at 15 keV.

It is an advantageous feature of the invention that the P-N diode can be centered under the gate stack and thus separated by a non-zero offset distance from the edge of the gate stack, so that it is better shielded by the gate stack than if the P-N junction were at one edge or the other of the gate stack. This advantage is realized because the P-N junction is defined by a resist aperture (FIG. 3 ), so that it can be located in the middle of the gate stack.

Referring now to FIG. 1, there is shown the completed diode. The exposed silicon areas have been silicided and contacts 52 , 54 and 56 have been formed making contact with suicides 52 ′, 54 ′ and 56 ′. Contact 52 will be conventionally tied to ground, but may lead elsewhere, depending on the circuit. Contact 54 will be tied to ground to prevent the lightly doped silicon of areas 32 and 36 from being inverted if stray charge on diode cover 44 sets up a strong enough field.

FIG. 7 illustrates the result of an alternative process, similar components having the same numbers. This process uses an “OP” resistor process to form resistors, typically by covering source/drain implants with an insulator (e.g. silicon nitride). Referring now to FIG. 8, a pattern of STI 25 has been formed to isolate the diode region from other devices, similar to FIG. 2 . Optionally, as shown in FIG. 9, the P-well implant may be used to dope the entire active area of the diode lightly p-type (as well as performing its primary function of doping the P-wells). Next, in FIG. 10, the resist used for source and drain NFET implants is opened above a portion of the diode region and the n+ implants form the cathode of the diode. As in FIG. 11, the region of the diode active area, displaced from the n+ doped region, is exposed and implanted p+ using the PFET source drain resist and implants. An insulator is deposited, silicon nitride being the preferred material, and patterned to leave the p-n junction region passivated as in FIG. 12 . Preferably, this insulator is deposited simultaneously with the deposition of a resistor-defining layer that blocks silicidation of a selected area and therefore forms a buried resistor below that layer. A silicide is next formed selectively on exposed silicon regions, typically titanium or cobalt silicide.

The invention could be used to form a diode in an N-type layer, in an undoped layer, or in a bulk silicon wafer, with appropriate changes in the implant species and dose.

While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims.