Inventor

Edward J. Nowak

Inventor

Essex Junction, VT, US

Overview

1979–2017

Patent span

Electricity

Primary field (CPC H)

Patents· 139 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices49%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%

H01LSemiconductor devices7%

G01RMeasuring electric variables3%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

H10BElectronic memory devices3%

H03KPulse technique2%

G01NInvestigating or analysing materials by determining their chemical or physical properties2%

B24BMachines, devices, or processes for grinding or polishing1%

PatentTitleYear

9,852,956Extraction of resistance associated with laterally diffused dopant profiles in CMOS devices2017 9,735,277'Partially dielectric isolated fin-shaped field effect transistor (FinFET)'2017 9,537,011'Partially dielectric isolated fin-shaped field effect transistor (FinFET)'2017 9,419,115'Junctionless tunnel fet with metal-insulator transition material'2016 9,418,982'Multi-layered integrated circuit with selective temperature coefficient of resistance'2016 9,419,016'Junctionless tunnel FET with metal-insulator transition material'2016 9,318,622'Fin-type PIN diode array'2016 9,276,002'Integrated circuit structure with bulk silicon FinFET'2016 9,170,165'Workfunction modulation-based sensor to measure pressure and temperature'2015 9,171,952'Low gate-to-drain capacitance fully merged finFET'2015 9,093,534'Dielectric filler fins for planar topography in gate level'2015 9,093,478'Integrated circuit structure with bulk silicon FinFET and methods of forming'2015 9,070,791'Tunable capacitor'2015 9,059,190'Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations'2015 8,929,039'Silicon controlled rectifier (SCR) clamp including metal insulator transition (MIT) resistor'2015 8,916,467'SOI radio frequency switch with enhanced signal fidelity and electrical isolation'2014 8,896,035'Field effect transistor having phase transition material incorporated into one or more components for reduced leakage current'2014 8,866,226'SOI radio frequency switch with enhanced electrical isolation'2014 8,709,833'Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations'2014 8,673,683'Graphene field effect transistor'2014 8,648,647'Determining current of a first FET of body connected FETs'2014 8,642,453'Schottky barrier diode and method of forming a Schottky barrier diode'2014 8,598,683'Semiconductor structure having varactor with parallel DC path adjacent thereto'2013 8,542,058'Semiconductor device including body connected FETs'2013 8,524,547'Fin-type field effect transistor'2013 8,492,823'High performance tapered varactor'2013 8,450,792'Structure and fabrication method of tunnel field effect transistor with increased drive current and reduced gate induced drain leakage (GIDL)'2013 8,420,468'Strain-compensated field effect transistor and associated method of forming the transistor'2013 8,412,487'Self heating monitor for SiGe and SOI CMOS devices'2013 8,377,810'Schottky barrier diode and method of forming a Schottky barrier diode'2013 8,354,309'Method of providing threshold voltage adjustment through gate dielectric stack modification'2013 8,350,269'Semiconductor-on-insulator (SOI) structure and method of forming the SOI structure using a bulk semiconductor starting wafer'2013 8,227,304'Semiconductor-on-insulator (SOI) structure and method of forming the SOI structure using a bulk semiconductor starting wafer'2012 8,217,497'FIN differential MOS varactor diode'2012 8,133,774'SOI radio frequency switch with enhanced electrical isolation'2012 8,131,225'BIAS voltage generation circuit for an SOI radio frequency switch'2012 8,129,773'Fin-type field effect transistor'2012 8,106,439'Fin-type field effect transistor'2012 8,106,455'Threshold voltage adjustment through gate dielectric stack modification'2012 8,030,687'Field effect transistor incorporating at least one structure for imparting temperature-dependent strain on the channel region and associated method of forming the transistor'2011 8,032,349'Efficient methodology for the accurate generation of customized compact model parameters from electrical test data'2011 8,026,131'SOI radio frequency switch for reducing high frequency harmonics'2011 7,999,320'SOI radio frequency switch with enhanced signal fidelity and electrical isolation'2011 7,964,466'FinFET transistor and circuit'2011 7,927,963'Integrated circuit structure, design structure, and method having improved isolation and harmonics'2011 7,862,233'Self heating monitor for SiGe and SOI CMOS devices'2011 7,843,005'SOI radio frequency switch with reduced signal distortion'2010 7,821,053'Tunable capacitor'2010 7,804,151'Integrated circuit structure, design structure, and method having improved isolation and harmonics'2010 7,777,276'FinFET transistor and circuit'2010 7,750,405'Low-cost high-performance planar back-gate CMOS'2010 7,732,286'Buried biasing wells in FETs (Field Effect Transistors)'2010 7,691,684'Fin-type antifuse'2010 7,666,775'Split poly-SiGe/poly-Si alloy gate stack'2010 7,645,650'Double gated transistor and method of fabrication'2010 7,579,897'Design structure for implementing oxide leakage based voltage divider network for integrated circuit devices'2009 7,560,798'High performance tapered varactor'2009 7,538,391'Curved FINFETs'2009 7,498,216'Method of forming high-performance CMOS SOI devices on hybrid crystal-oriented substrates'2009 7,492,029'Asymmetric field effect transistors (FETs)'2009 7,485,506'Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETS'2009 7,479,410'Hybrid-orientation technology buried n-well design'2009 7,470,578'Method of making a finFET having suppressed parasitic device characteristics'2008 7,462,916'Semiconductor devices having torsional stresses'2008 7,456,426'Fin-type antifuse'2008 7,405,458'Asymmetric field transistors (FETs)'2008 7,406,397'Self heating monitor for SiGe and SOI CMOS devices'2008 7,368,355'FinFET transistor and circuit'2008 7,361,556'Method of fabricating semiconductor side wall fin'2008 7,348,642'Fin-type field effect transistor'2008 7,329,937'Asymmetric field effect transistors (FETs)'2008 7,314,794'Low-cost high-performance planar back-gate CMOS'2008 7,307,467'Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices'2007 7,298,161'Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability'2007 7,291,886'Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs'2007 7,288,445'Double gated transistor and method of fabrication'2007 7,271,453'Buried biasing wells in FETS'2007 7,265,417'Method of fabricating semiconductor side wall fin'2007 7,256,458'Doubly asymmetric double gate transistor structure'2007 7,250,656'Hybrid-orientation technology buried n-well design'2007 7,250,666'Schottky barrier diode and method of forming a Schottky barrier diode'2007 7,177,619'Dual gate FinFET radio frequency switch and mixer'2007 7,163,864'Method of fabricating semiconductor side wall fin'2007 7,115,920'FinFET transistor and circuit'2006 7,101,741'Dual double gate transistor and method for forming'2006 7,087,477'FinFET SRAM cell using low mobility plane for cell stability and method for forming'2006 7,064,019'Implanted asymmetric doped polysilicon gate FinFET'2006 7,064,413'Fin-type resistors'2006 7,060,553'Formation of capacitor having a Fin structure'2006 7,052,958'FinFET CMOS with NVRAM capability'2006 7,011,980'Method and structures for measuring gate tunneling leakage parameters of field effect transistors'2006 6,995,412'Integrated circuit with capacitors having a fin structure'2006 6,995,456'High-performance CMOS SOI devices on hybrid crystal-oriented substrates'2006 6,992,354'FinFET having suppressed parasitic device characteristics'2006 6,987,289'High-density FinFET integration scheme'2006 6,980,009'Structure for measurement of capacitance of ultra-thin dielectrics'2005 6,967,351'Finfet SRAM cell using low mobility plane for cell stability and method for forming'2005 6,960,806'Double gated vertical transistor with different first and second gate materials'2005 6,953,726'High-density split-gate FinFET'2005 6,894,326'High-density finFET integration scheme'2005 6,891,359'Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability'2005 6,888,199'High-density split-gate FinFET'2005 6,888,187'DRAM cell with enhanced SER immunity'2005 6,864,136'DRAM cell with enhanced SER immunity'2005 6,841,834'Doubly asymmetric double gate transistor structure'2005 6,815,277'Method for fabricating multiple-plane FinFET CMOS'2004 6,812,075'Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same'2004 6,800,905'Implanted asymmetric doped polysilicon gate FinFET'2004 6,794,718'High mobility crystalline planes in double-gate CMOS technology'2004 6,750,487'Dual double gate transistor'2004 6,727,118'Power distribution design method for stacked flip-chip packages'2004 6,720,231'Fin-type resistors'2004 6,692,998'Integrated high quality diode'2004 6,664,582'Fin memory cell and method of fabrication'2003 6,662,350'FinFET layout generation'2003 6,657,252'FinFET CMOS with NVRAM capability'2003 6,657,259'Multiple-plane FinFET CMOS'2003 6,642,090'Fin FET devices from bulk semiconductor and method for forming'2003 6,635,970'Power distribution design method for stacked flip-chip packages'2003 6,610,576'Method for forming asymmetric dual gate transistor'2003 6,583,469'Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same'2003 6,492,212'Variable threshold voltage double gated transistors and method of fabrication'2002 6,476,483'Method and apparatus for cooling a silicon on insulator device'2002 6,462,585'High performance CPL double-gate latch'2002 6,456,082'Method for polysilicon crystalline line width measurement post etch in undoped-poly process'2002 6,406,962'Vertical trench-formed dual-gate FET device structure and method for creation'2002 6,329,690'Method and apparatus to match semiconductor device performance'2001 6,300,228'Multiple precipitation doping process'2001 6,271,565'Asymmetrical field effect transistor'2001 6,083,794'Method to perform selective drain engineering with a non-critical mask'2000 6,064,263'DTCMOS differential amplifier'2000 5,982,225'Hot electron compensation for improved MOS transistor reliability'1999 5,635,869'Current reference circuit'1997 5,587,604'Contacted body silicon-on-insulator field effect transistor'1996 5,336,637'Silicide interconnection with Schottky barrier diode isolation'1994 5,250,834'Silicide interconnection with schottky barrier diode isolation'1993 5,242,524'Device for detecting an end point in polishing operations'1993 5,213,655'Device and method for detecting an end point in polishing operation'1993 4,179,168'Display device having a locking mechanism'1979

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1979Based in Cudahy, WI, US· patent location history

1993–2017Patents assigned to IBM (135)· patent assignee history

1993–2017Based in Essex Junction, VT, US· patent location history

1993–2004Based in Essex, VT, US· patent location history

2012–2015Patents assigned to NOWAK EDWARD J (23)· patent assignee history

2012–2014Patents assigned to BOTULA ALAN B (4)· patent assignee history

2012–2013Patents assigned to GREENE BRIAN J (3)· patent assignee history

2012–2014Patents assigned to JOSEPH ALVIN J (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	135	1993–2017
NOWAK EDWARD Jself	23	2012–2015
BOTULA ALAN B	4	2012–2014
GREENE BRIAN J	3	2012–2013
JOSEPH ALVIN J	3	2012–2014

Locations

Location	Patents	Span
Essex Junction, VT, US	133	1993–2017
Essex, VT, US	5	1993–2004
Cudahy, WI, US	1	1979