Semiconductor package and method for forming same

The present invention relates in general to a semiconductor package and a method of forming the semiconductor package, and more particularly to a semiconductor package and method of forming the semiconductor package using a removable carrier.

As is known, a semiconductor die does not lend itself readily to handing and mounting on, for example, a printed circuit board (PCB). Typically, a semiconductor die is packaged in a semiconductor package, which can be conveniently handled and mounted both manually and by automated machines. In conventional semiconductor packaging a semiconductor die is mounted on a leadframe. A leadframe provides a portion for mounting the die, often called a flag portion, and has lead portions having an inner and an outer end. The leadframe holds the flag portion and the lead portions in position relative to each other while the die is mounted on the flag portion, and wires connected between the die and the inner ends of the lead portions.

The die, the flag portion, inner ends of the lead portions, and the wires, are then encapsulated in mould compound to form a semiconductor package with the outer ends of the lead portions and outer portions of the lead frame extending from the semiconductor package. After encapsulation, the outer portion of the leadframe is cut to separate the semiconductor package from the leadframe. Prior to the step of encapsulation the leadframe provides support to hold the die and lead portions in position. However, after encapsulation, the mould compound provides the support. In addition, after separation, the outer portions of the leadframe are discarded.

Hence, the leadframe performs a temporary support function, which results in the additional step of separation, and also results in waste of leadframe material.

Embodiments of the invention will now be more fully described, by way of example, with reference to the drawings of which:

FIG. 1 shows a side sectional view of a semiconductor package in accordance with the present invention;

FIGS. 2A-2E shows a side sectional view of the semiconductor package in FIG. 1 being formed;

FIG. 3 shows a side sectional view of the semiconductor package in FIG. 1 with a heat sink attached;

FIG. 4 shows a side sectional view of a semiconductor package in accordance with the present invention;

FIGS. 5A-5F shows a side sectional view of the semiconductor package in FIG. 4 being formed; and

FIG. 6 shows a side sectional view of the semiconductor package in FIG. 4 with a heat sink attached.

FIG. 1 shows a semiconductor package 8 with at least one semiconductor die 10 , at least one interconnect 20 , and encapsulant 30 , such as mould compound. The die 10 has a mounting surface 12 and an interconnect surface 14 , where the interconnect surface 14 is opposite the mounting surface 12 . The mounting surface 12 forms the back of the semiconductor die 10 and usually comprises a layer of metallisation, which typically forms an electrical ground terminal for electronic circuitry in the die 10 , and also provides a surface for mounting the die 10 . The interconnect surface 14 has at least one die pad 16 . The die pad 16 is formed by a layer of metallisation. When connection to the pad 16 is by soldering, then the layer of metallisation is made of solder.

An intermediate portion 17 between the mounting surface 12 and the interconnect surface 14 forms the body of the die 10 with side surfaces 18 . The side surfaces 18 can be shaped to have contours 19 . The contours 19 provide improved mould locking which increases the mechanical strength with which the encapsulant 30 holds the die 10 in the package 8 . In addition, the contours 19 improve sealing between the die 10 and the encapsulant 30 . The improved seal reduces penetration of moisture into the package, and this advantageously results in improved package reliability.

The interconnect 20 has an inner end 22 which connects to the at least one die pad 16 , an outer end 24 for external connection, and an intermediate portion 26 . The intermediate portion 26 extends between the inner end 22 and the outer end 24 and forms the body of the interconnect 20 . The intermediate portion 26 can be shaped to allow for convenient handling by a pick and place machine. In addition, the intermediate portion 26 can include mould lock features 27 to improve mould locking between the encapsulant 30 and the interconnect 20 , which brings the same benefits of increased mechanical strength and improved sealing described earlier. The interconnect 20 can be made of tinplated copper pieces. The encapsulant 30 encapsulates the die 10 and the interconnects 20 . In order to ensure good mould locking between the encapsulant 30 and both the die 10 and interconnect 20 , it is important that the encapsulant 30 which is used has characteristics which enables the mould compound 30 to flow into the contours 19 , and also to fill the mould lock features 27 during encapsulation.

In FIG. 2A, the semiconductor die 10 is placed with its mounting surface 12 on a semiconductor mounting surface 40 of a carrier 42 . The carrier 42 is a polymer and the semiconductor mounting surface 40 holds the semiconductor die 10 releasably, i.e. such that the die 10 and the mounting surface 12 can be separated after encapsulation. In addition, the carrier 42 is able to withstand the rigors of encapsulation, while securing the die 10 firmly during other processes prior to encapsulation. In order to secure the die 10 , the mounting surface 40 may be specially provided with adhesive or the entire surface of the carrier may be provided with a layer of adhesive. Alternatively or additionally, the carrier 42 can have die holding features, such as clips (not shown) to hold the die 10 onto the carrier 42 .

In FIG. 2B, the interconnect 20 is mounted on the die 10 by connecting the inner ends 22 to the die pads 16 . This can be accomplished in a variety of ways including by solder, epoxy, thermosonic bonding, or thermocompression bonding.

In FIG. 2C, the encapsulant 30 encapsulates the die 10 and the interconnects 20 to form the semiconductor package 8 on the carrier 42 . This can be accomplished by enclosing the carrier 42 , the die 10 and the interconnects 20 within a mould cavity 41 that is formed between two mould pieces i.e. an upper mould piece 45 and a lower mould piece 47 . Upper and lower surfaces of the mould cavity, 48 and 49 respectively, will be of such dimension as to sandwich the die 10 , the interconnects 20 , and the carrier 42 between them. Resilience of the carrier 42 ensures a good seal between the mould pieces 45 and 47 during the encapsulation process.

In FIG. 2D, the semiconductor package 8 is formed on the carrier 42 after encapsulation and is shown after moving the mould pieces 45 and 47 away.

In FIG. 2E, the semiconductor package 8 is removed from the carrier 42 . This may be accomplished using a pick and place operation, where the package 8 is picked off the carrier 42 by a pick and place arm, for example. Alternatively, a simple stripping process where a removal blade is positioned to wedge the packages off the carrier as the carrier and blade are moved in opposite directions relative to each other, may be employed.

The encapsulant 30 surrounds the intermediate portion 17 of the die 10 and the intermediate portion 26 of the interconnect 20 , and fills the contours 19 and the mould lock features 27 . However, the mounting surface 12 of the die 10 and the outer end 24 of the interconnect 20 is not encapsulated, i.e. the mounting surface 12 of the die 10 and the outer end 24 of the interconnect 20 are left exposed.

In FIG. 3, a heatsink 50 is coupled to the mounting surface 12 of the die 10 . This may be accomplished by solder, heat conductive epoxy, or bonding. The heatsink 50 can be made of tin-plated copper and may be shaped to suit particular heat dissipation and mounting requirements.

In FIG. 4 a semiconductor package 60 has at least one semiconductor die 62 , at least one connector 63 , at least one interconnect 64 , and encapsulant 65 , such as mould compound. The die 62 has a mounting surface 61 and an interconnect surface 66 , where the interconnect surface 66 is opposite the mounting surface 61 . The mounting surface 61 forms the back of the semiconductor die 62 and usually comprises a layer of metallisation, which typically forms an electrical ground terminal for electronic circuitry in the die 62 , and also provides a surface for mounting the die 62 . The interconnect surface 66 has at least one die pad 68 . The die pad 68 is formed by a layer of metallisation.

An intermediate portion 70 between the mounting surface 61 and the interconnect surface 66 forms the body of the die 62 with side surfaces 71 . The side surfaces 71 can be shaped to have contours 72 . The contours 72 provide improved mould locking which increases the mechanical strength with which the encapsulant 65 holds the die 62 in the package 60 . In addition, the contours 72 improve sealing between the die 62 and the encapsulant 65 . The improved seal reduces penetration of moisture into the package 60 , and this results in improved package reliability.

The interconnects 64 each have an inner end 73 for connecting to the at least one die pad 68 , an outer end 74 for external connection, and an intermediate portion 26 . The intermediate portion 76 extends between the inner end 73 and the outer end 74 and forms the body of the interconnect 64 . The intermediate portion 76 can be shaped to allow for convenient handling by a pick and place machine, for example. In addition, the intermediate portion 76 can include mould lock features 78 to improve the mechanical strength with which the encapsulant 65 holds the interconnects 64 , to bring the same benefits of increased mechanical strength and improved sealing described earlier. The interconnects 64 can be made of tin plated copper pieces.

The connectors 63 each have a die end 80 for coupling to the die pad 68 , and an interconnect end 82 for connecting to the inner end 73 of the interconnects 64 . The connectors 63 are typically lengths of wire, either gold, aluminum or copper wire, whose ends are bonded to the die pad 68 and the inner end 73 to form an electrical connection therebetween. The encapsulant 65 encapsulates the die 62 , the connectors 63 and the interconnects 64 .

In FIG. 5A, the semiconductor die 62 is placed with its mounting surface 61 on a semiconductor mounting surface 90 of a carrier 92 . The carrier 92 is a polymer and the semiconductor mounting surface 90 holds the semiconductor die 62 releasably, i.e. such that the die 62 and the mounting surface 90 can be separated after encapsulation. In addition, the carrier 92 is able to withstand the rigors of encapsulation, while securing the die 62 firmly during other processes prior to encapsulation. In order to secure the die 62 , the mounting surface 90 may be specially provided with adhesive or the entire surface of the carrier maybe provided with a layer of adhesive.

In FIG. 5B, the interconnect 64 is placed with its outer end 74 on an interconnect mounting surface 94 of a carrier 92 . A pick and place process, typically performed by an automated machine, could be used to place the interconnect 64 on the interconnect mounting surface 94 .

In FIG. 5C, the connectors 63 are connected between the die pad 68 and the inner end 73 of the interconnects 64 . When ultrasonic thermocompression bonding is used to connect the connector 63 , comprising a length of wire, typically gold wire, a free end of a supply the wire (not shown) is formed into a ball (not shown). The ball forms the die end 80 which is bonded to the die pad 68 . A length of the wire is then supplied and the end of the length of wire, which forms the interconnect end 82 , is bonded to the inner end 73 and the wire severed from the supply.

In FIG. 5D, the encapsulant 65 encapsulates the die 62 , the connectors 63 , the interconnect mounting surface 94 , and the interconnects 64 to form the semiconductor package 60 on the carrier 92 . This can be accomplished by enclosing the mounting surface 90 of the carrier 92 , the die 62 , the connectors 63 , and the interconnects 64 , within a mould cavity 100 that is formed between two mould pieces i.e. an upper mould piece 101 and a lower mould piece 102 . Upper and lower surfaces of the mould cavity, 104 and 106 respectively, will be of such dimension as ensure the connectors 63 are completely encapsulated. Resilience of the carrier 92 ensures a good seal between the mould pieces 10 1 and 102 during encapsulation.

In FIG. 5E, the semiconductor package. 60 is formed on the carrier 92 after encapsulation and is shown after moving the mould pieces 10 1 and 102 , away.

In FIG. 5F, the package 60 is removed from the carrier 92 . The encapsulant 65 surrounds the intermediate portion 70 of the die 62 , the connectors 63 , and the intermediate portion 78 of the interconnects 64 . However, the mounting surface 61 of the die 62 and the outer ends 74 of the interconnects 64 are not encapsulated, i.e. the mounting surface 61 of the die 62 and the outer ends 74 of the interconnects 64 , are left exposed.

In FIG. 6, a heatsink 110 is coupled to the mounting surface 61 of the die 62 . This may be accomplished by solder, heat conductive epoxy, bonding, etc. The heatsink 110 can be made of tin-plated copper.

Hence, the present invention provides a semiconductor package which overcomes, or at least reduces the above-mentioned problems of the prior art. It will be appreciated that although only one particular embodiment of the invention has been described in detail, various modifications and improvements can be made by a person skilled in the art without departing from the scope of the present invention.