USPatent applicationPatented

Low consumption oscillator

Granted 29 Apr 2003 · 3 office actions

Assignee: STMicroelectronics

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Attorney: Attorney · Log in to unlock

Inventors: Richard Ferrant · Examiner: Arnold Kinkead · AU 2817 · TC 2800

Application· this page
9627814
filed 28 Jul 2000
Publication
Not published
not published
Patent
US 6,556,092
granted 29 Apr 2003

Life of the application

13 dated events
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Abstract

A low consumption oscillator having an inverter connected to a high supply potential and to a low supply potential via two respective resistors, with the resistors formed of capacitors having strong leakages.

Description

5 parts
›TECHNICAL FIELD

The present invention relates to a quartz oscillator using an inverter in CMOS technology, and more specifically to a low consumption oscillator.

›BACKGROUND OF THE INVENTION

FIG. 1 shows such an oscillator that includes an inverter 8 formed of a P-channel MOS transistor MP 1 and of an N-channel MOS transistor MN 1 , series connected between a high supply potential Vdd and a low supply potential GND. The gates of transistors MP 1 and MN 1 are interconnected and form input A of the inverter. Output B of the inverter, which is also the output of the oscillator, is sampled from the drains of transistors MP 1 and MN 1 . A quartz crystal 10 is connected in parallel with a resistor 12 between the input and the output of inverter 8 . Further, two capacitors 14 and 16 respectively connect the input and the output of inverter 8 to low supply potential GND.

Such an oscillator consumes a power proportional to the oscillation frequency, this consumption being essentially due to the simultaneous conduction of transistors MP 1 and MN 1 upon transitions of the output signal.

FIG. 2 shows a solution currently used to reduce the consumption of an oscillator of the type in FIG. 1 . Transistors MP 1 and MN 1 , instead of being directly connected to potentials Vdd and GND, are connected to these potentials via respective resistors 18 and 20 .

With this configuration, the switching currents of inverter 8 are decreased proportionally to the value of resistors 18 and 20 . However, the amplitude of the output signal decreases all the more as resistors 18 and 20 have high values. This amplitude decrease does not affect the oscillator operation, but an amplifier 22 however has to be provided to bring the peak levels of the oscillator's signal back to levels close to the supply potentials to generate an exploitable logic signal.

Accessorily, capacitors 24 and 25 are connected in parallel with resistors 18 and 20 , which provides a smoothing of the voltage across transistors MP 1 and MN 1 and a decrease of the dynamic output impedance of the inverter.

Resistors 18 and 20 can be chosen with particularly high values without affecting the oscillator operation. A problem however is the forming of resistors of high value in an integrated circuit. In an integrated circuit, a resistor is formed of a polysilicon track having a length proportional to the value of the resistor. To form resistors of proper value for a low consumption oscillator of the type in FIG. 2, the polysilicon tracks would take up a non-negligible surface area.

›SUMMARY OF THE INVENTION

The disclosed embodiments of the present invention provide an oscillator with a particularly low power consumption that does not require a resistor occupying a significant surface area.

To achieve the foregoing, the disclosed embodiments of the present invention provide a low power consumption oscillator comprising an inverter connected to a high supply potential and to a low supply potential via two respective resistors. The resistors are formed of capacitors with a strong leakage.

According to an embodiment of the present invention, the oscillator output is connected to an amplifier intended to provide logic levels from the output levels of the oscillator.

According to an embodiment of the present invention, the amplifier includes several stages, each including two transistors connected in series between the high and low supply potentials, the gate of a first transistor of each stage being connected to the output of the preceding stage, and the gates of the second transistors of two consecutive stages being respectively connected to the input and to the output of said inverter.

The foregoing features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.

›BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1, previously described, shows a conventional quartz oscillator;

FIG. 2, previously described, shows a conventional low consumption quartz oscillator;

FIG. 3 shows an embodiment of a low consumption quartz oscillator according to the present invention; and

FIG. 4 shows a particularly advantageous example of an amplifier used in the oscillator of FIG. 3 .

›DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 3, the same elements as shown in FIGS. 1 and 2 are designated by the same reference numbers. According to the disclosed embodiments of the present invention, resistors 18 and 20 of the oscillator of FIG. 2 have been replaced with capacitors 18 C and 20 C of a specific type. No other element is provided to connect transistors MP 1 and MN 1 to supply potentials Vdd and GND.

According to the present invention, capacitors 18 C and 20 C are formed to have strong leakages with respect to conventional capacitors formed in the same technology. A conventional capacitor typically has a leakage resistance on the order of 10 12 Ω/μm 2 . This resistance is so high that the oscillator cannot operate. Conversely, capacitors 18 C and 20 C are, according to the present invention, denatured to have strong leakages, for example, by doping their dielectric with impurities. Leakage resistances on the order of 100 to 1000 MΩ, which enable the oscillator operation, are thus obtained. The exact value of the resistances is of no importance within the above range (it can be controlled to 20-25%). However, the two capacitors must substantially have the same leakage resistance, to have a symmetrical signal. This is easy to guarantee in a same batch of integrated circuits.

The resistances obtained with this solution are much higher than those that can be obtained with conventional methods (smaller than 10 MΩ). Further, the capacitance of capacitors 18 C and 20 C is of little importance. In particular, the capacitors can be chosen to have the smallest possible size, to occupy a negligible surface.

Capacitors 18 C and 20 C accessorily perform the function of capacitors 24 and 25 of FIG. 2 and thus may be used as a charge tank.

The amplitude of the output signal of the oscillator of FIG. 3 is particularly small. For example, in an oscillator supplied under 2 V and operating at a 50-MHz frequency with capacitors 18 C and 20 C having a leakage resistance of 100 MΩ, the output signal has a peak-to-peak amplitude of 300 mV. As for the circuit of FIG. 2, the output signal is provided to an amplifier 22 intended for bringing the amplitude of the signal close to the supply voltage. Amplifier 22 must be able to operate at high frequency while having a low consumption.

FIG. 4 shows an example of an amplifier fulfilling these conditions. This amplifier includes a succession of stages, each of which is comprised of a P-channel MOS transistor MP 2 and of an N-channel MOS transistor MN 2 connected in series between high supply potential Vdd and low supply potential GND. The gate of the transistor MP 2 of a stage is connected to the output of the preceding stage, that is, to the drains of transistors MP 2 and MN 2 of the preceding stage. The gates of the transistors MN 2 of two successive stages are respectively connected to input A and to output B of inverter 8 of FIG. 3 . The gate of the transistor MP 2 of the first stage is connected to the output of this same stage. The amplifier output is sampled from the output of the last stage. It may be differentially sampled from the outputs of the last two stages.

The number of stages of the amplifier determines its gain. The gain is substantially equal to 2 n , where n is the number of stages.

The quiescent current of each stage can be chosen to be particularly small. It is determined by the size of transistors MP 2 and MN 2 and the common mode voltage on input terminals A and B, this common mode voltage being half the supply voltage if the leakage resistances of capacitors 18 C and 20 C are equal.

Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. For example, one of the input terminals of the amplifier of FIG. 4, instead of receiving the output or input signal of inverter 8 , may receive a constant voltage equal to the common mode voltage.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereof.

Claims as granted

17 claims

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Classifications

7 codes
IPC · International Patent Classification
Section H — Electricity
  • H03K3/03
  • H03K3/012
USPC · US Patent Classification
331/116.FE331/158331/366331/109331/116.R

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File wrapper

⤢ drag to zoomJul 2000Jan 2001Jul 2001Jan 2002Jul 2002Jan 2003Jul 2003USPTOApplicantNon-final rejectionResponse after non-finalFinal rejectionNotice of allowanceRequest for continued examinationResponse after non-finalNotice of allowance
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Pendency
2.8 y
1,005 days filing → grant
Office actions
3
non-final + final
Responses
2
1 RCE
Interviews
2
examiner interview summaries
Examiner
Arnold Kinkead
art unit 2817 · TC 2800
Citations: 4 back · 2 forward

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