LexDanaLexDanabeta
Inventor

Richard Ferrant

Inventor
Esquibien, FR

Overview

85→
Patents
1987–2018
Patent span
Electricity
Primary field (CPC H)

Patents· 85 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores46%
H10DInorganic electric semiconductor devices15%
H10BElectronic memory devices12%
H03KPulse technique7%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
H01LSemiconductor devices3%
G06FElectric digital data processing2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
B82YSpecific uses or applications of nanostructures1%
PatentTitleYear
10,110,235Look-up table architecture20189,621,168'Look-up table'20179,576,642'Memory device with dynamically operated reference circuits'20179,496,877'Pseudo-inverter circuit with multiple independent gate transistors'20169,490,264'Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said device'20169,479,174'Tristate gate'20169,390,771'Circuit and method for sensing a difference in voltage on a pair of dual signal lines, in particular through equalize transistor'20169,251,871'Sense amplifier with dual gate precharge and decode transistors'20169,230,662'Eprom cell'20169,225,237'Charge pump circuit comprising multiple—gate transistors and method of operating the same'20159,159,400'Semiconductor memory having staggered sense amplifiers associated with a local column decoder'20159,135,964'Differential sense amplifier without switch transistors'20159,111,593'Differential sense amplifier without dedicated precharge transistors'20159,035,474'Method for manufacturing a semiconductor substrate'20158,953,399'Differential sense amplifier without dedicated pass-gate transistors'20158,664,712'Flash memory cell on SeOI having a second control gate buried under the insulating layer'20148,652,887'Multi-layer structures and process for fabricating semiconductor devices'20148,654,602'Pseudo-inverter circuit on SeOI'20148,625,374'Nano-sense amplifier'20148,575,697'SRAM-type memory cell'20138,508,289'Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer'20138,455,938'Device comprising a field-effect transistor in a silicon-on-insulator'20138,432,216'Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer'20138,384,425'Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrate'20138,358,552'Nano-sense amplifier'20138,325,506'Devices and methods for comparing data in a content-addressable memory'20128,310,866'MRAM device structure employing thermally-assisted write operations and thermally-unassisted self-referencing operations'20128,305,803'DRAM memory cell having a vertical bipolar injector'20128,304,833'Memory cell with a channel buried beneath a dielectric layer'20128,266,494'Bus with error correction circuitry'20128,223,582'Pseudo-inverter circuit on SeOI'20127,994,560'Integrated circuit comprising a transistor and a capacitor, and fabrication method'20117,817,466'Semiconductor array including a matrix of cells and a method of making a semiconductor array having a matrix of cells'20107,733,693'Semiconductor memory device and method of operating same'20107,359,229'Semiconductor memory device and method of operating same'20087,212,432'Resistive memory cell random access memory device and method of fabrication'20077,200,032'MRAM with vertical storage element and field sensor'20077,187,581'Semiconductor memory device and method of operating same'20077,180,160'MRAM storage device'20077,180,801'Memory circuit with shared redundancy'20077,161,863'DRAM refreshment'20077,130,206'Content addressable memory cell including resistive memory elements'20067,085,156'Semiconductor memory device and method of operating same'20067,085,153'Semiconductor memory cell, array, architecture and device, and method of operating same'20067,068,533'Resistive memory cell configuration and method for sensing resistance values'20067,057,916'Small size ROM'20067,020,016'Random access memory cell and method for fabricating same'20066,995,997'Cache cell with masking'20066,934,202'Memory circuit with dynamic redundancy'20056,920,075'Amplifier for reading storage cells with exclusive-OR type function'20056,808,990'Random access memory cell and method for fabricating same'20046,801,467'DRAM cell refreshment method and circuit'20046,798,681'DRAM'20046,765,405'Protection circuit against voltage or current spikes, and clock circuit using a protection circuit of this kind'20046,583,459'Random access memory cell and method for fabricating same'20036,563,749'Dynamic memory circuit including spare cells'20036,556,092'Low consumption oscillator'20036,538,942'Process for controlling a read access for a dynamic random access memory and corresponding memory'20036,535,987'Amplifier with a fan-out variable in time'20036,489,810'Highly reliable programmable monostable'20026,477,673'Structure and method with which to generate data background patterns for testing random-access-memories'20026,455,884'Radiation hardened semiconductor memory with active isolation regions'20026,452,841'Dynamic random access memory device and corresponding reading process'20026,421,799'Redundancy correction ROM'20026,373,741'Memory circuit architecture'20026,360,294'Device and method for simultaneously reading/rewriting a dynamic random-access memory cell using a plurality of amplifiers and isolation circuitry'20026,316,986'Method and device for voltage multiplication'20016,215,706'Fast structure dram'20016,208,551'Memory circuit architecture'20016,205,077'One-time programmable logic cell'20016,091,650'Redundancy for low remanence memory cells'20006,018,486'Reading method and circuit for dynamic memory'20006,005,818'Dynamic random access memory device with a latching mechanism that permits hidden refresh operations'19995,982,679'Memory circuit with dynamic redundancy'19995,973,985'Dual port SRAM cell having pseudo ground line or pseudo power line'19995,898,622'Read circuit for memory'19995,862,091'Memory accessible in read mode only'19995,570,313'Memory insensitive to disturbances'19965,506,807'Memory circuit with redundancy'19965,469,485'Frequency divider'19955,410,506'Memory integrated circuit with protection against disturbances'19954,879,693'Device for the self-synchronization of the output circuits of a memory using a three-state gate'19894,877,483'Method for contact between two conductive or semi-conductive layers deposited on a substrate'19894,761,767'High reliability integrated circuit memory'19884,707,810'Integrated circuit memory'1987

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1987–1989Based in Aix en Provence, FR· patent location history
1995–2006Based in Saint Ismier, FR· patent location history
1999–2000Based in Berkeley, CA, US· patent location history
2000–2007Patents assigned to ST MICROELECTRONICS SA (22)· patent assignee history
2001–2007Based in Crolles, FR· patent location history
2004–2018Based in Esquibien, FR· patent location history
2012–2018Patents assigned to SOITEC SILICON ON INSULATOR (28)· patent assignee history
2012–2016Patents assigned to FERRANT RICHARD (22)· patent assignee history
2012–2016Patents assigned to MAZURE CARLOS (17)· patent assignee history
2012–2016Patents assigned to NGUYEN BICH-YEN (8)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SOITEC SILICON ON INSULATOR282012–2018
FERRANT RICHARDself222012–2016
ST MICROELECTRONICS SA222000–2007
MAZURE CARLOS172012–2016
NGUYEN BICH-YEN82012–2016
Locations
LocationPatentsSpan
Esquibien, FR482004–2018
Saint Ismier, FR201995–2006
Crolles, FR62001–2007
Aix en Provence, FR41987–1989
Berkeley, California, US21999–2000