Voltage dependent capacitor configuration for higher soft error rate tolerance

The invention relates generally to integrated circuits. In particular, the invention relates to reducing soft errors in integrated circuits.

The operating voltage of a high-speed microprocessor is being reduced as process technology scales. For example, microprocessor device dimensions are shrinking and integrated circuit (IC) chips are operating at increasing frequencies. As a result, IC chips are becoming more susceptible to external interferences. Interference may be caused by cosmic rays, or by spurious noise, for example.

These noise sources can cause soft errors in memories and storage elements in the IC chips when they are used at high altitudes in aerospace applications. Also, the noise sources can cause soft errors in IC chips even at ground levels. A conventional capacitor does not adjust itself to fight a node charge injection by noise sources. Consequently, storage elements in data paths of an IC chip, such as static latches and dynamic gates for example, are becoming susceptible to the soft error rate (SER) caused by noise sources.

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:

FIG. 1 is an ideal capacitance-to-voltage (CV) curve to hold both ‘0’ and ‘1’ states.

FIG. 2 is a practical CV curve to hold both ‘0’ and ‘1’ states.

FIG. 3 is an embodiment of an SER tolerant capacitor.

FIG. 4 is a CV Curve of the capacitor shown in FIG. 3 .

FIG. 5 is an embodiment of a low area SER tolerant capacitor.

FIG. 6 is a CV Curve of the capacitor shown in FIG. 5 .

A voltage dependent capacitor to provide higher soft error rate (SER) tolerance is disclosed. The capacitor has a capacitance that changes in response to noise. In one embodiment, the capacitor includes a pMOS (p metal oxide semiconductor) capacitor connected in parallel to an nMOS (n metal oxide semiconductor) capacitor. In another embodiment, the capacitor includes an nFET(n Field Effect Transistor)-in-nWell device.

The voltage dependent capacitor achieves a higher soft error rate tolerance by adding an explicit capacitance on a susceptible storage node. The voltage dependent capacitor can have a high capacitance to area ratio, so that the node is able to hold both ‘0’ and ‘1’ states on the node in case of external interference, such as a cosmic ray, for example. The capacitor also enables the node to efficiently hold a state in case of spurious noise attacks. The voltage dependent capacitor thus hardens the storage nodes from external interference, which increases the SER tolerance of the nodes. The voltage dependent capacitor further requires less area on an IC chip than conventional capacitors.

A capacitance structure that exhibits voltage dependency is significantly better in its ability to hold a node at a given voltage value. A capacitor that is able to hold both ‘0’ and ‘1’ states in spite of noise can have an ideal voltage-dependent capacitance as shown in FIG. 1. A capacitor having this capacitance-to-voltage (CV) curve holds both ‘0’ and ‘1’ states well. If noise is injected into the capacitor, the change in voltage across the capacitor will automatically increase the capacitance value, which prevents noise from changing the state of the capacitor.

For example, suppose the capacitor is in the ‘0’ state having voltage V 0 and capacitance C OX . If an external noise V n is injected into the capacitor, the capacitance increases to C n . This external noise is not sufficient to change the value of the capacitor from the ‘0’ state to the ‘1’ state. The capacitor returns to C OX and maintains the ‘0’ state, thus successfully fighting the noise injection. However, a capacitor having an ideal capacitance to voltage curve may consume a significant amount of area on an IC.

A practical capacitance-to-voltage (CV) curve is shown in FIG. 2. A capacitor having this CV curve increases its capacitance value when the noise injection is in the unwanted range, which is the-range R between the ‘0’ state and the ‘1’ state, as shown in FIG. 2 . For example, if the capacitor is in the ‘1’ state, and the noise injection is V n , the capacitance increases from C OX to C n , thus enabling the capacitor to resist the noise injection and maintain the ‘1’ state.

This CV curve is not ideal, because outside of the unwanted range R, the capacitance decreases as voltage increases. However, the noise that is outside of the unwanted range does not change the state of the capacitor. Therefore, a capacitor having a CV curve as shown in FIG. 2 can occupy less area on an IC than a capacitor having an ideal CV curve of FIG. 1 .

One embodiment of a voltage dependent capacitor that approximates the practical CV curve of FIG. 2 to provide soft error rate (SER) tolerance is shown in FIG. 3 . Two capacitors, such as an nMOS capacitor 310 and a pMOS capacitor 320 , for example, are connected in parallel.

In the embodiment shown in FIG. 3, the depletion-inversion sloping curves of the nMOS and pMOS devices can be shifted towards ‘0’ (for the nMOS device, for example) and ‘1’ (for the pMOS device, for example), as shown in FIG. 4, to achieve a CV curve that enables the voltage dependent capacitor to resist noise and maintain its current state. (V tn is the threshold voltage of the nMOS device and V tp is the threshold voltage of the pMOS device). Because both of the capacitors are in depletion-inversion, as shown in FIG. 4, source and drain diffusions are required. The voltage dependent capacitor of FIG. 3 yields high capacitance for its entire range of operation, which results in a higher effective capacitance per area.

The voltage dependent capacitor shown in FIG. 3 provides a practical voltage dependent, SER hardening capacitor. However, a node in a circuit that needs to be held at ‘0’ as well as ‘1’ could use an alternate voltage dependent capacitor as shown in FIG. 5, that requires less area than the embodiment of FIG. 3 . The ‘0’ state may be approximately 0 volts, and the ‘1’ may be approximately 1 volt, for example.

FIG. 5 shows an embodiment of a voltage dependent capacitor having an nFET-in-nWell device 500 . An n-well 520 is placed on a p-substrate 530 . A signal is input to the device 500 through an n-type polysilicon gate input 510 . An internal implicit n-well resistance R 1 connects gate 510 to n+ well tap 540 through the n-well 520 .

The n-doped source and drain diffusions are eliminated without significant loss in capacitive performance. This reduces the amount of area of the capacitor and increases the SER tolerance of the corresponding node. Thus, this embodiment of a voltage dependent capacitor can be used to provide an area efficient SER hardening device.

An example of an ideal capacitance-voltage curve for the voltage dependent capacitor of FIG. 5 is shown FIG. 6 . This alternative embodiment displays a positive voltage dependency at the ‘0’ state, as shown in FIG. 6 . In this embodiment, the capacitor has a weak negative dependency at the ‘1’ state.

Furthermore, as shown in FIG. 5, the resistance R 1 can be adjusted by changing the position of the n+ well tap connected to Vss. This changes the internal inherent resistance of the capacitor device. The resistance adjustment can be utilized in frequency response tuning.

This embodiment provides several significant features. The voltage dependence of this capacitor yields higher holding capacity, and the lack of diffusions saves area as well as reduces SER collection area. The adjustable internal resistance enables frequency tuning. Furthermore, this capacitor provides an excellent node capacitance for high soft error tolerance.

Thus, several embodiments of a voltage dependent capacitor to provide soft error rate tolerance are disclosed. In one embodiment, a parallel n-p voltage dependent capacitor is used to protect a node from noise if area is not a significant concern. Alternatively, an nFET-in-nWell voltage dependent capacitor is used if reducing the area of the capacitor is important.

The voltage dependent capacitor has an appropriate voltage dependency, positive in the case of a ‘0’ state and negative in the case of a ‘1’ state, to provide a node capacitance for high soft error tolerance. This voltage dependent capacitor thus enables the speed of microprocessors to be increased. Furthermore, the voltage dependent capacitor directly supports 30% supply voltage scaling and development of process technologies for low voltage, high performance and low power CMOS (complimentary metal oxide semiconductor) circuits. Latched circuits can be introduced into integrated circuits without being adversely affected by soft error rates by using voltage dependent capacitors. The fabrication of the voltage dependent capacitors disclosed herein is compatible with current processing technology.

These and other embodiments of the present invention may be realized in accordance with the teachings described herein and it should be evident that various modifications and changes may be made to these teachings without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense and the invention measured only in terms of the claims.