Temperature and process independent CMOS circuit

1. Field of the Invention

This invention relates to analog circuits such as multipliers, adaptive filters, function generators, modulators, and neural networks. More particularly, this invention relates to compensation circuits incorporated with analog circuits to offset deviation in operation of the analog circuit due to variations in temperature and process.

2. Description of Related Art

Analog function circuits such as multipliers, adaptive filters, function generators, modulators, and neural networks, as is known in the art, produce a voltage output, which is proportional to an arithmetic function of two voltage inputs. As semiconductor processing has improved, more and varied circuits are formed on a semiconductor substrate. This has mandated the creation of libraries of analog function circuits or analog function cores. FIG. 1 shows a system diagram of an analog function core. There are two differential voltage inputs νx, νy, and one differential voltage output νout. A load resistor RL is connected between the inverted and non-inverted output the differential voltage output νout. The differential output voltage νout is developed across a load resistor, RL and is determined by the formula:

νout=kF(ν x ν y )  EQ. 1

where:

k is a constant of proportionality or scaling

factor.

F is the arithmetic function to be performed on the two differential input signals νx and νy.

The load resistor RL of FIG. 1 can be formed of the two load resistors RL 1 and RL 2 as shown in FIG. 2 . The load resistor RL 1 is connected between the inverting output (−) of the differential output voltage νout and the common mode biasing voltage source Vcm. The load resistor RL 2 is connected between the non-inverting output (+) of the differential output voltage vout and the common mode biasing voltage source Vcm.

The voltage level present at the inverted (−) output terminal of the differential output νout is determined as:

νout−=Iout 1 *RL 1 +Vcm where:

I out1 is the output current and is determined as a function of the two differential input signals

νx and νy.

RL 1 is the resistance value of the load resistor. Conversely, the voltage level present at the non-inverted (+) output terminal of the differential output νout is determined as:

νout+=Iout 2 *RL 2 +Vcm

where:

I out2 is the output current and is determined as a function of the two differential input signals

νx and νy.

RL 2 is the resistance value of the load resistor.

FIG. 3 shows an example of an analog function circuit implemented as a voltage multiplier with differential voltage inputs and a voltage output across a load resistor. The non-inverting input νx+ of the first differential voltage input νx is connected to the gate of one of the n-type metal oxide semiconductor (MOS) transistors M 1 of a parallel connected pair of n-type MOS transistors M 1 and M 2 . The gate of the second n-type MOS transistor M 2 of the parallel connected pair of n-type MOS transistors M 1 and M 2 is connected to the inverting input νx− of the first differential voltage input νx. The commonly connected sources of the parallel connected pair of n-type MOS transistors M 1 and M 2 are connected to a first terminal of a current source Ib 3 . The second terminal of the current source Ib 3 is connected to a ground reference point. The commonly connected drains of the parallel connected pair of n-type MOS transistors M 1 and M 2 are connected to a first terminal of a current source Ib 1 . The second terminal of the current source Ib 1 is connected to a power supply voltage source V DD . The junction of the commonly connected drains of the parallel connected pair of n-type MOS transistors M 1 and M 2 and the first terminal of a current source Ib 3 form the output terminal containing the inverted output (−) of the differential output voltage νout.

The non-inverting input νy+ of the first differential voltage input νy is connected to the gate of one of the n-type metal oxide semiconductor (MOS) transistors M 3 of a parallel connected pair of n-type MOS transistors M 3 and M 4 . The gate of the second n-type MOS transistor M 4 of the parallel connected pair of n-type MOS transistors M 3 and M 4 is connected to the inverting input νy− of the second differential voltage input νy. The commonly connected sources of the parallel connected pair of n-type MOS transistors M 3 and M 4 are connected to a first terminal of a current source Ib 4 . The second terminal of the current source Ib 4 is connected to a ground reference point. The commonly connected drains of the parallel connected pair of n-type MOS transistors M 3 and M 4 are connected to a first terminal of a current source Ib 2 . The second terminal of the current source Ib 2 is connected to a power supply voltage source V DD . The junction of the commonly connected drains of the parallel connected pair of n-type MOS transistors M 3 and M 4 and the first terminal of a current source Ib 2 form output terminal containing the non-inverted output (+) of the differential output voltage vout.

The load resistor RL 1 is connected between the inverting output (−) of the differential output voltage νout and the common mode biasing voltage source Vcm. The load resistor RL 2 is connected between the non-inverting output (+) of the differential output voltage vout and the common mode biasing voltage source Vcm.

The gates of the parallel connected pair of n-type MOS transistors M 1 and M 2 and the gates of the parallel connected pair of n-type MOS transistors M 3 and M 4 are biased externally with a constant voltage source VB (not shown) to cause the parallel connected pair of n-type MOS transistors M 1 and M 2 and the parallel connected pair of n-type MOS transistors M 3 and M 4 to operate in the saturation region. This insures that any voltage developed from the drains to the sources of the parallel connected pair of n-type MOS transistors M 1 and M 2 or the parallel connected pair of n-type MOS transistors M 3 and M 4 does not effect the saturation drain-to-source current Ids through the parallel connected pair of n-type MOS transistors M 1 and M 2 or the parallel connected pair of n-type MOS transistors M 3 and M 4 .

The drain-to-source saturation current Ids sat of each of the parallel connected pair of n-type MOS transistors M 1 and M 2 or the parallel connected pair of n-type MOS transistors M 3 and M 4 is found by the formula:

Ids sat =K(V GS −V T ) 2

where:

VGS is the gate-to-source of each MOS transistor.

VT is the threshold voltage at which MOS transistor begins to conduct or turn-on.

K is a process constant found as the function K = μ s  ( C ox 2 )  ( W L )

where:

μ s is the mobility of the bulk doped semiconductor material that forms the channel.

C ox is the capacitance of the gate oxide of the MOS transistors. ( W L )

is the width-to-length ratio of the MOS transistors.

As can be shown from Einstein's Relationship, the mobility μ s of the semiconductor material is dependent upon the absolute temperature of operation. Further, any changes in the process that effects the doping of the semiconductor material will further change the value of the mobility μ s of the semiconductor material. Additionally, process changes may effect the geometric values of the width-to-length ratio ( W L ) ,

as well as the thickness of the insulating material that forms the gate oxide, which will change the values of the capacitance C ox .

It can be shown that the output currents I out1 and I out2 can be calculated by the formula: I out1 = I out2 = μ n  ( C ox )  ( W L ) * v x * v y

where:

μ n is the mobility of the bulk doped semiconductor material that forms the channel.

C ox is the capacitance of the gate oxide of the parallel connected pair of n-type MOS transistors M 1 and M 2 and the parallel connected pair of n-type MOS transistors M 3 and M 4 . ( W L )

is the width-to-length ratio of the parallel connected pair of n-type MOS transistors M 1 and M 2 and the parallel connected pair of n-type MOS transistors M 3 and M 4 .

Thus, the voltage level present at the inverted (−) output terminal of the differential output νout is determined as: Vout += I out1 * RL1 = μ n  C ox  ( W L ) * v x * v y * RL1 Eq .    3

and the voltage level present at the non-inverted (+) output terminal of the differential output νout is determined as: Vout -= I out2 * RL2 = μ n  C ox  ( W L ) * v x * v y * RL2 . Eq .    4

An object of this invention is to provide an analog integrated circuit such as a multiplier, adaptive filter, function generator, modulator, or neural network whose output voltage signal is independent from variations in temperature and process.

Another object of this invention is to provide a compensation circuit in connection with or integrated with an analog circuit such as a multiplier, adaptive filter, function generator, modulator, or neural network to make the output signal of the analog circuit not vary with changes in temperature and manufacturing process.

To accomplish these and other objects a temperature and process independent analog integrated circuit has an analog integrated function core circuit. The function core circuit has a first differential pair of input terminals to receive a first input signal, a second differential pair of input terminals to receive a second input signal, and a differential pair of output terminals. The differential pair of output terminals contains an output signal that is a function of a scaling constant, the first input signal, and the second input signal.

The analog integrated circuit has a first and a second loading device. The first loading device has a first terminal connected to an inverted terminal of the differential pair of output terminals, a second terminal connected to a common mode voltage terminal, and a third terminal. A loading control voltage at the third terminal controls a loading on a voltage signal present at the inverted terminal by the first loading device. The second loading device has a first terminal connected to an non-inverted terminal of the differential pair of output terminals, a second terminal connected to the common mode voltage terminal, and a third terminal. The loading control voltage also at the third terminal controls the loading on a voltage signal present at the non-inverted terminal by the second loading device. The first and second loading devices in the preferred embodiment are MOS transistors of a second conductivity type and are biased by a loading device controller to operate in a linear operation region of the first and second loading devices.

The loading device controller within the analog integrated circuit compensates for changes in voltage level of the output signal due to variations in temperature and variations in manufacturing process within the function core circuit. The loading device controller has a loading control voltage terminal to provide the loading control voltage. The loading device controller has a first MOS transistor of a first conductivity type with a gate connected to a first control bias voltage source, a source connected to the ground reference point, and a drain. The loading device controller has a second MOS transistor of the first conductivity type with a source connected to the drain of the first MOS transistor of the first conductivity type, a gate, and a drain. A first MOS transistor of the second conductivity type has a source connected to the common mode voltage terminal, a drain connected to the second MOS transistor of the first conductivity type, and gate connected to the loading control voltage terminal. A first differential amplifier has an inverting input connected to a second control bias voltage source, a non-inverting input connected to the connection of the drain of the first MOS transistor of the second conductivity type and the drain of the second MOS transistor of the first conductivity type, and an output connected to the gate of the first MOS transistor of the second conductivity type and forms the loading control voltage terminal. The voltage present at the connection of the drain of the first MOS transistor of the second conductivity type and the drain of the second MOS transistor of the first conductivity type is maintained at a voltage level equal to a voltage level of the second bias control voltage source. A second differential amplifier has an inverting input connected to the connection of the drain of the first MOS transistor of the first conductivity type and the source of the second MOS transistor of the first conductivity type, a non-inverting input connected to a third biasing control voltage source, and an output connected to the gate of the second MOS transistor of the first conductivity type. The voltage at the connection of the drain of the first MOS transistor of the first conductivity type and the source of the second MOS transistor of the first conductivity type is maintained at the voltage level of the third biasing voltage source.

Further, the analog integrated core circuit has a biasing circuit. The biasing circuit has the common mode voltage terminal to provide a common mode voltage to the first and second loading devices and in communication with the compensation circuit provide the first, second and third control bias voltage sources.

The bias circuit includes a bandgap referenced current source. The bandgap referenced current source provides a reference current that is independent of temperature. A current mirror has a reference terminal that is responsive to the reference current source, a first terminal coupled to the compensation circuit to provide a first current proportional to the reference current and second terminal to provide a second current proportional to the reference current.

The bias circuit has a first resistor connected to the first terminal of the current mirror. A threshold voltage generator is connected between a second terminal of the first resistor and a ground reference point such that the first bias voltage source is provided to the first to the compensation circuit.

A voltage divider is connected between the second terminal of the current mirror and the ground reference point. The voltage divider has a first terminal to provide the second bias voltage source to the compensation circuit and a second terminal to provide a third bias voltage source to the compensation circuit. A voltage buffer has an input terminal that is in communication with the connection of the second terminal of the current mirror and the voltage divider. An output terminal is connected to the common mode voltage terminal to provide the common mode voltage source in response to a fourth biasing voltage present at the connection of the second terminal of the current mirror and the voltage divider.

If the analog integrated core circuit is a multiplier circuit, it has a first and a second parallel connected pair of MOS transistors of a first conductivity type. A gate of one MOS transistor of the first parallel connected pair of MOS transistors is connected to an inverting input of the first differential pair of input terminals. A gate of the other MOS transistor of the parallel connected MOS transistors is connected to a non-inverting input of the first differential pair of input terminals. Commonly connected drains are connected to the inverted terminal of the differential pair of output terminals. Likewise, gate of one MOS transistor of the second parallel connected pair of MOS transistors is connected to an inverting input of the second differential pair of input terminals. A gate of the other MOS transistor of the parallel connected MOS transistors is connected to a non-inverting input of the second differential pair of input terminals. Commonly connected drains are connected to the non-inverted terminal of the differential pair of output terminals. A first biasing constant current source is connected between a power supply voltage source and the commonly connected drains of the first parallel connected MOS transistors, and a second biasing constant current source is connected between commonly connected sources of the first parallel connected MOS transistors and a ground reference point. A third biasing constant current source is connected between a power supply voltage source and the commonly connected drains of the second parallel connected MOS transistors, and a fourth biasing constant current source is connected between commonly connected sources of the second parallel connected MOS transistors and a ground reference point.

FIGS. 1 and 2 are system block diagrams of a two-input voltage multiplier of the prior art.

FIG. 3 is a schematic of an analog multiplier of the prior art.

FIGS. 4 a - 4 d are schematics of an analog function including a temperature and process compensation circuit and a voltage biasing circuit of this invention.

Refer now to FIG. 4 a for a discussion of an analog integrated circuit of this invention. The analog function core circuit as described in FIG. 1, has two differential input signals ν 1 and ν 2 that are combined according to an arithmetic function to form a differential output voltage signal νout. The magnitude of the differential output voltage signal νout is shown in EQ. 1, above.

To develop the output voltage νout, the load resistors RL 1 and RL 2 of FIG. 4 a are implemented as two p-type MOS transistors M 5 and M 6 configured to act as active load devices. The source of the active load device RL 1 is connected to the inverted output (−) of the analog function core circuit and the drain is connected to the bias circuit to receive the common mode voltage Vcm. The gate is biased to a voltage level Vg, such that the active load device will operate in the linear region of the MOS device characteristics. The source of the active load device Rp 2 is connected to the non-inverted output (+) of the analog function core circuit and the drain is connected to the bias circuit to receive the common mode voltage Vcm. The gate is also biased to a voltage level Vg, such that the active load device RL 2 will also operate in the linear region of the MOS device characteristics.

If the analog function core circuit is implemented as the analog multiplier, as discussed above in FIG. 3, using n-type MOS transistors, as shown, the active load devices RL 1 and RL 2 are implemented as the p-type MOS transistors M 5 and M 6 to provide compensation for changes in the currents I out and I out2 due to fluctuations in temperature and changes in fabrication process.

The resistance of the loading devices RL 1 and RL 2 can be shown to be: RL1 = RL2 = 1 μ p  C ox  ( W L ) p  ( v g - v Tp ) Eq .    5

where:

μ p is the mobility of the bulk doped semiconductor material that forms the channel of the p-type MOS transistors M 5 and M 6 .

C ox is the capacitance of the gate oxide of the p-type MOS transistors M 5 and M 6 . ( W L )

is the width-to-length ratio of the p-type MOS transistors M 5 and M 6 .

v g is the voltage at the gate of the p-type MOS transistors M 5 and M 6 .

v Tp is the threshold voltage of the p-type MOS transistors M 5 and M 6 .

The compensation circuit has an output connected to the gates of the loading devices RL 1 and RL 2 to provide the biasing voltage Vg to maintain the loading devices in their linear operating region. The compensation circuit further has an input terminal connected to the bias circuit to receive the common mode voltage source Vcm.

The compensation circuit, as shown in FIG. 4 b , has a p-type MOS transistor M 7 that acts as a third loading device Rp. The source of the third loading device Rp is connected to the bias circuit to receive the common mode voltage Vcm. The compensation circuit has a differential amplifier U 2 , with an output that provides the biasing voltage level Vg. The drain of the loading device Rp is connected to the non-inverting input (+) of the differential amplifier U 2 . The inverting input (−) of the differential amplifier U 2 is connected to the biasing circuit that provides the a biasing voltage Vc 3 . The voltage level of the biasing voltage Vc 3 is set between 100 mV and 200 mV lower than the desired voltage level of the common mode voltage Vcm.

The compensation circuit has an n-type MOS transistor M 8 with its drain connected to the drain of the p-type loading device Rp. The compensation circuit further has a differential amplifier U 1 with an output connected to the gate of the n-type MOS transistor M 8 .

The compensation circuit finally has an n-type MOS transistor M 9 that acts as an n-type loading device Rn, with a drain connected to the source of the n-type MOS transistor M 8 and the non-inverting input of the differential amplifier U 1 . The inverting input of the differential amplifier U 1 is connected to the biasing circuit that provides a biasing voltage Vc 2 . The biasing voltage Vc 2 is set to a voltage level of approximately 150 mV above the ground reference point. The source of the n-type loading device Rn is connected to the ground reference point. The gate of the n-type loading device Rn is connected to the bias circuit, which provides a biasing voltage Vc 1 .

The decoupling capacitor C c is connected between the output terminal of the compensation circuit that provides the biasing voltage level Vg and the ground reference point. The decoupling capacitor C c is sufficiently large to filter any high frequency noise present at the output terminal of the compensation circuit that provides the biasing voltage level Vg.

The biasing voltage level Vg at the output of the differential amplifier U 2 forces the voltage level V 3 at the non-inverting input of the differential amplifier U 2 to be set to the voltage level of the biasing voltage source Vc 3 . The current I p is then determined as: I p = Vcm - V 3 Rp

where:

V 3 is the voltage level at the source of the p-type loading device Rp and is equal to the voltage level of the biasing voltage Vc 3 .

I p is the current through the p-type loading device Rp.

Rp is the effective resistance of the p-type loading device M 10 and is determined to be:    Rp = 1 μ p * C ox * ( W L ) p2 * ( Vg - V Tp )

where:

μ p is the mobility of the p-type semiconductor material.

C ox is the capacitance of the gate oxide of the p-type loading device Rp. ( W L ) p2

is the width to length ratio of the gate of the p-type loading device Rp.

V TP is the threshold voltage of the p-type loading device Rp.

As is apparent, the value of the current Ip is equal to the value of the current In through the n-type loading device Rn. The current In is determined as: I n = V n Rn

where:

V n is equal to the voltage level of the biasing voltage Vc 2 .

Rn is the resistance of the loading device and is determined as: Rn = 1 μ n * C ox * ( W L ) n * ( Vc1 - V Tn )

where:

μ n is the mobility of the n-type semiconductor material.

C ox is the capacitance of the gate oxide of the p-type loading device Rn. ( W L ) n

is the width to length ratio of the gate of the n-type loading device Rn.

V Tn is the threshold voltage of the n-type loading device Rn.

Therefore, the by setting the two currents Ip and In equal and solving for the voltage Vg−V Tp of FIG. 5 can be shown to equal: Vg - V Tp = [ μ n μ p ]  [ ( W L ) n2 ( W L ) p2 ]  ( Vc1 - V Tn )  Vc2 Vcm - Vc3 . Eq .    6

The differential amplifier U 2 will set the biasing voltage level Vg to the voltage necessary to force the voltage level V 3 to equal the voltage of the biasing voltage level Vc 3 .

By substituting Eq. 6 for the Vg−V Tp in Eq. 5 and then substituting Eq. 5 into Eq. 3 and Eq. 4, differential output voltage signal vout can be shown to equal: Vout = [ ( W L ) n ( W L ) p  ( W L ) p2 ( W L ) n2 ] * [ Vcm - Vc3 ( Vc1 - v tn )  Vc2 ]  v x * v y

As is known in the art, the mobilities μ p and μ n are dependent on temperature thus the common mode voltage becomes insensitive to the effects of temperature. Also, any changes of the geometric and process dependent parameters ( ( W L ) , V T )

are cancelled. Thus any changes in the common mode voltage Vcm and the biasing voltage level Vg are compensated to correct any variations in the output voltage level νout of the multiplier core due to temperature and voltage. Further, the voltages Vcm, Vc 1 , Vc 2 , and Vc 3 are constructed to be referenced to the bandgap of silicon to maintain their constant reference.

FIG. 4 c illustrates the bias circuit of this invention that generates the voltages Vcm, Vc 1 , Vc 2 , and Vc 3 . The input of the bias circuit is a bandgap reference voltage source V bg . The bandgap reference voltage source provides an accurate voltage source referenced to the bandgap voltage of the bulk semiconductor (silicon). The operational amplifier U 3 and the MOS transistor M 14 are configured such that the voltage V bg2 at the source of the MOS transistor M 14 is equal to the bandgap reference voltage V bg . This insures that the current I ref flowing through the resistor R 2a is constant.

The p-type MOS transistors M 10 , M 11 , and M 12 are configured and designed as current mirrors. The currents I 1 and I 2 are proportional to the current I ref and the relative width-to-length ratios ( W L )

of the p-type MOS transistors M 10 , M 11 , and M 12 .

The n-type MOS transistor M 13 has its gate and drain connected to form a diode. The current I 1 is set such that the drain-to-source voltage is the threshold voltage V T of the n-type MOS transistor M 13 . The biasing voltage Vc 1 is set at a voltage level of approximately the threshold voltage of the n-type loading device Rn 2 plus a constant voltage V const and is equal to approximately 0.6V. The constant voltage V const is equal to the value of the resistor R 3 multiplied by the current I 1 .

The common mode voltage V′cm is determined by the current I 2 flowing through the resistors R 2b , R 3 , and R 4 and is equal to:

V′cm=I 2 (R 2 b +R 3 +R 4 ).

The operational amplifier U 4 is configured as a unity gain buffer to prevent additional loading on the current I 2 . The output of the operational amplifier U 4 performs as the voltage source for the common mode voltage Vcm.

The biasing voltage Vc 2 is determined by the current I 2 flowing through the resistor R 2b and is found as:

Vc 2 =I 2 *R 2 b.

The biasing voltage Vc 3 is determined by the current I 2 flowing through the resistor R 2b and R 3 and is found as:

Vc 3 =I 2 *R 2 b+R 3 .

To those skilled in the art it will be apparent that a design incorporating n-type MOS load resistors for p-type MOS multipliers can be derived by reversing the roles of the loading devices Rp and Rn in the embodiment as shown in FIG. 4 b above.

While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.