Semiconductor device with STI sidewall implant

Trench isolation has been used in the semiconductor industry to reduce circuit topography and better isolate adjacent semiconductor devices. In a typical process of forming shallow trench isolation (STI), a thermally oxidized film is formed on the surface of a shallow trench. The trench is then filled with a dielectric material, for example oxide. A high density plasma process typically deposits the oxide used to fill the trenches and forms isolations. The high density plasma process may create charge trapping along the trench sidewall edge. In addition, it can produce an increase in the hot carrier sensitivity of PMOSFET devices. The enhanced hot carrier sensitivity is due to increased trapping efficiency of electron injection into the STI edge during the hot carrier and can result in the activation of a parasitic edge parasitic PMOSFET device. Thus, there is a need to reduce the STI process induced hot carrier sensitivity in PMOSFETs.

Additionally, a nitride liner is sometimes formed on the thermally oxidized film in the STI. The nitride liner has been shown to be a highly effective oxygen diffusion barrier. Thus, the nitride liner may be formed to prevent oxidation of a silicon sidewall of a collar region of a storage trench. Moreover, the nitride liner prevents dislocations in the active areas of devices.

However, use of the nitride liner can cause some problems. The nitride liner has been shown to be a source of charge trapping, which leads to unacceptable levels of junction leakage in support circuitry. The charge trapping is the result of electron injection into the nitride liner. Charge trapping occurs in the nitride liner mainly due to process induced plasma charging.

The presence of the nitride liner and the resulting increase in electron trapping enhances the hot carrier sensitivity of buried channel PMOSFETs. Many methods of handling charge trapping have been proposed for other types of devices. Most of the methods address the problem by reducing the charge trapped in the nitride liner to improve isolation. For example, U.S. Pat. No. 5,747,866 to Ho et al. describe a structure which limits charge trapping. Ho et al. describe a crystalline RTN nitride liner deposited at greater than 1050° C. to lower the density of trapping centers. However, no satisfactory solutions have been provided for improving hot carrier reliability.

Thus, there is a need for a semiconductor device and manufacturing process that addresses the issue of charge trapping and the degraded hot carrier reliability currently associated with known processes.

A semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. After formation of the oxide liner, first regions of the semiconductor substrate are masked, leaving second regions thereof exposed. N-type devices are to be formed in the first regions and p-type devices are to be formed in the second regions. N-type ions may then be implanted into sidewalls of the trenches in the second regions. The mask is stripped and formation of the semiconductor device may be carried out in a conventional manner. The n-type ions are preferably only implanted into sidewalls where PMOSFETs are formed.

The present invention will now be further described in the following pages of specification when taken in conjunction with the attached drawings, in which:

FIG. 1A is a cross-section of a semiconductor wafer explaining a process according to an embodiment of the invention;

FIG. 1B shows the wafer of FIG. 1A with trenches formed therein;

FIG. 1C shows the wafer of FIG. 1B with an oxide liner formed in the trenches;

FIG. 1D shows the wafer of FIG. 1C with a mask on the NMOSFET region;

FIG. 1E illustrates implantation of ions into the wafer of FIG. 1D;

FIG. 1F illustrate the wafer of FIG. 1E with a nitride liner formed in the trench;

FIG. 1G shows the wafer of FIG. 1C with the trench partially filled with a dielectric;

FIG. 2 shows a cross-section of a semiconductor device formed according to an embodiment of the present invention; and

FIG. 3 shows a top view of a semiconductor device formed according to an embodiment of the present invention.

The present invention provides a method of forming semiconductor devices with improved hot carrier reliability. Ions are implanted into sidewalls of trenches. The implanted ions form a doped layer that prevents electron injection into the trench. The invention can be used in any situation where NMOSFETs and PMOSETs are formed, for example in any CMOS application. In these instances, the ions are implanted into the STI sidewall in areas where PMOSFETs are formed in order to improve hot carrier reliability.

The invention is preferably implemented in the context of a DRAM array NMOSFET and will be describe below in this context. However, as mentioned above, the invention may also be used in connection with the formation of many other semiconductor devices. Typically, a DRAM array NMOSFET includes NMOSFET array devices formed in a p-well and NMOSFET and PMOSFET support devices formed in support regions. The NMOSFETs and PMOSFETs are usually formed in array and support regions on the same semiconductor substrate. STI is used to isolate the various array regions and support regions of the semiconductor substrate and the semiconductor devices formed thereon from one another. As discussed above, the STI usually includes a nitride liner formed in the trench and a high density plasma oxide filling the trench. Electron injection into trench sidewalls during the hot carrier stresses results into a degradation on PMOSFETs used as support circuitry in the DRAM.

The present invention reduces or prevents this degradation of hot carrier reliability by implanting n-type dopants into the PMOSFET active area (AA) sidewall. It has been observed that this sidewall implant improves the hot carrier reliability. The formation of the sidewall implant can be easily incorporated into current processes used in forming DRAM arrays. In a typically DRAM process, the semiconductor substrate is divided into array regions and support regions. Trenches are etched into the semiconductor substrate. An AA oxide may then be formed in the trench. A doped layer, preferably formed by implanting n-type dopants, is also formed in the AA sidewall.

Forming the n-type layer in AA sidewalls where NMOSFETs are to be formed would render the NMOSFET array useless. Therefore ion implantation should be prevented in the AA sidewalls where NMOSFETs are formed. The n-type layer is preferably only implanted into the AA sidewalls of buried channel PMOSFETs formed in the support region.

Thus, after formation of the AA oxide, the array regions of the semiconductor substrate should be masked, leaving the support regions exposed. N-type ions may then be implanted into the AA sidewall in the support regions, while the array regions are protected. The doping concentration of the n-types ions implanted will depend on the doping concentration of the n-well and whether a surface channel or a buried channel device is being formed. The dose of the implant should be higher than the doping concentration of the n-well to have any effect and should extend deeper into the substrate than any buried channel depth. If a surface channel device is being formed, the depth of the implantation should not be a concern. The ion implantation forms an n-type layer in STI sidewalls in the support region of semiconductor substrate. The mask over the array region is then stripped and formation of the semiconductor device may be carried out in a conventional manner. As mentioned above, the n-type ions are preferably only implanted into the PMOSFET AA sidewall. The n-type layer reduces hot carrier induced electron injection into the trench sidewall, thus improving the hot carrier reliability.

Turning now to FIGS. 1A-1F, a method according to an embodiment of the present invention will now be described. A semiconductor substrate 11 is provided. Normally, a pad oxide film 12 about 3 nm to 8 nm thick is formed on the substrate 11 . A pad nitride film 13 about 100 nm to 250 nm thick is usually then formed on top of the pad oxide film 12 , resulting in the structure shown in FIG. 1 A. Next, the pad nitride film 13 , pad oxide film 12 and substrate 11 are selectively etched by a known etching process. Trenches 14 are thereby formed, as shown in FIG. 1 B. The trenches 14 have sidewalls 16 and bottoms 17 . When forming a DRAM, the semiconductor substrate 11 is usually divided into a plurality of array and NMOSFET regions 20 and a plurality of PMOSFET support regions 22 . The arrangement of the trenches 14 is determined, in part, so that these regions 20 , 22 are isolated from each other. Consequently, one of the trenches 14 will separate the array and NMOSFET region 20 from the support PMOSFET region 22 as shown in FIG. 1 B. Additionally, trenches 14 define element active regions therebetween where semiconductor devices may be formed, as describe below. The above process is well known and can be carried out using conventional techniques known to one skilled in the art.

As shown in FIG. 1C, an oxide liner 15 may be formed in a conventional manner on surfaces of the trench 14 . The oxide liner 15 is typically provided to passivate the surface of the substrate 11 and is usually less than 10 nm thick. Preferably, the oxide liner 15 formed only on surfaces inside the trench 14 , that is on sidewalls 16 and bottoms 17 . Oxide liner 15 is also used here as a sacrificial oxide for ion implantation into the STI sidewalls 16 .

Next, ion implantation into the STI sidewalls is performed. The ion implantation should be carried out only in trenches in the PMOSFET support region 22 . Accordingly, mask 24 may be formed over the semiconductor substrate 11 , as shown in FIG. 1 D. The mask 24 is preferably formed over the array region 20 and any other portion of the semiconductor substrate 11 where NMOSFETs are to be formed. The support region 22 of the substrate 11 should not be covered by mask 24 and is exposed. The mask 24 may be a layer of resist, for example, tungsten nitride. N-type ions are then implanted into the exposed surfaces of the semiconductor substrate 11 . As shown in FIG. 1E, n-type ions are implanted into sidewalls 16 and bottom 17 of trenches 14 . In order to have the greatest effect, the concentration of implanted ions should be highest in the STI sidewalls 16 . The amount of ions implanted into the bottom 17 of the trench 14 is not of great concern. Consequently, the ion implantation should be an angled implant to direct the ions into sidewalls 16 . An angled ion implant at 30 degrees with a dose of about 4−5×10 12 cm −2 at an energy of 30 keV is preferred in this context. As a result of this implantation, an n-type layer 26 is formed in substrate 11 . After ion implantation, the mask 24 may be stripped exposing the array region 20 .

As discussed above, a nitride liner can be used in a DRAM process present in STI structures. In a preferred embodiment, a nitride liner 28 is formed after the ion implantation. The nitride liner 28 may be formed on the oxide liner 15 . The nitride liner 28 is preferably a non-crystalline layer formed by LPCVD at 700°-800° C. The LPCVD process is well known to one skilled in the art. Additionally, the nitride layer 28 may be formed both inside the trench 14 and on the pad nitride layer 13 , as shown if FIG. 1 F. If a nitride liner is provided, the n-type layer 26 should be formed in all areas of the trench 14 where the nitride liner is to be formed.

In an additional embodiment, the trench 14 may be partially filled with a dielectric before implantation of the n-type ions into the sidewalls. In the above-described process, the trench 14 is partially filled after forming the oxide liner 15 . FIG. 1G illustrates the support region 22 of FIG. 1C with the trench partially filled with oxide 31 . The array region 20 is then masked with resist 24 and the ion implantation is carried out. The oxide 31 partially filling the trench 14 prevents ion implantation into the bottom 17 of the trench 14 . Top parts 18 of the sidewall 16 remain exposed become doped with the n-type impurities. Thus, the ions are implanted only at the top of the sidewalls. The STI is then completely filled after the sidewall implant.

Formation of the DRAM may then be completed in a known manner. For example, as shown in FIG. 2, trenches 14 are filled with an oxide 31 to form isolations. Element active regions are defined on the semiconductor substrate in areas between the isolations. Source/drain regions 34 a, b are formed in substrate 11 in the element active areas and gate conductor 33 is formed on gate oxide 32 resulting in the MOSFET shown in FIG. 2 .

FIG. 3 is a top view of a transistor formed according to an embodiment of the invention. Source/drain regions 34 a, b are traversed by gate conductor 33 . As STI regions 31 surround the transistor for isolation, n-type layer 26 is preferably formed surrounding the source/drain regions 34 a, b as shown in FIG. 3 .

Consequently, a device with improved hot carrier reliability and method of forming the same is provided. N-type dopants are implanted into the PMOSFET AA sidewall. The sidewall implant improves the hot carrier reliability of buried channel PMOSFETs, even in the presence of a nitride liner. As discussed above, the invention is not limited to used in forming DRAM arrays. The invention may be used whenever NMOSFET and PMOSFET device are formed. A block mask preferably protects the NMOSFETs and n-type ions are implanted into STI sidewalls of the PMOSFETs.

The foregoing description of the invention illustrates and describes the present invention. Additionally, the disclosure shows and describes only the preferred embodiments of the invention, but as aforementioned, it is to be understood that the invention is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings, and/or the skill or knowledge of the relevant art. The embodiments described hereinabove are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other, embodiments and with the various modifications required by the particular applications or uses of the invention. Accordingly, the description is not intended to limit the invention to the form disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments.