Method to differentiate source/drain doping by using oxide slivers

1. Field of the Invention

The present invention relates to integrated circuit manufacturing. More particularly, the present invention relates to reducing the steps in making Metal Oxide Semiconductor Field-Effect Transistor(hereinafter, MOSFET) source drain implants with extensions.

2. Discussion of the Related Art

Typically, a MOSFET circuit is fabricated from a single-crystal silicon substrate of a silicon wafer, which may be doped p-type or n-type. The significant steps in manufacturing a MOSFET circuit are described briefly in the following as background information. Initially, the surface of the silicon wafer is exposed to steam or dry oxygen at high temperature to form an oxide layer on the substrate. Subsequently, a layer of polycrystalline silicon (polysilicon hereafter) is deposited and patterned to form a gate structure. Thereafter, the source and the drain regions are formed by implanting dopants into the silicon substrate. However, if the source and the drain regions have extensions, and a different depth or doping levels are desired for such extensions, separate steps are required to form the source and drains and the extensions. However, high efficiency can be achieved if both the source and the drain regions and their respective extensions can be formed in one step using only one mask.

The present invention provides a method for manufacturing the source and the drain regions and their extensions in a single masking step. The method manufactures MOSFET devices in which the source and drain regions are associated with extension regions having depth and dopant levels different from those of the source and the drain regions.

A method of the present invention includes making a channel-shaped oxide structure surrounding the polysilicon gate. The oxide structure forms an implantation barrier for subsequent dopant implantation into the extension regions. Thus, when the source and drain regions are implanted at a given energy level, the extension regions are also implanted, but to a lower depth and a lower dopant concentration relative to the depth and dopant concentration of the source and the drain regions.

FIG. 1 illustrates an intermediate structure 10 under a manufacturing process, in accordance with one embodiment of the present invention.

FIGS. 2 a - 2 j illustrate steps the manufacturing process forming structure 10 of FIG. 1 in accordance with the present invention.

FIG. 1 illustrates an intermediate structure 10 , in a process for manufacturing MOSFETs, in accordance with one embodiment of the present invention. In a typical integrated circuit, millions of MOSFETs are formed in a single silicon die, and many silicon dies are formed. Structure 1 O is drawn for illustrative purpose only and not to scale. Delineations between the various doped regions are illustrative rather than realistic depictions. As shown in FIG. 1, structure 10 includes silicon substrate 12 , which is doped either n-type or p-type. On top of silicon substrate 12 is provided gate oxide layer 14 . Polysilicon gate structure 16 is formed on gate oxide layer 14 . On opposite sides of gate structure 16 is formed source region 18 and drain region 20 , including their respective extensions 22 A and 22 B. In this embodiment, source region 18 and extension 22 A and drain region 20 and extension 22 B have different dopant levels and extensions 22 A and 22 B are shallower than corresponding source region 18 and drain region 20 . FIG. 1 also shows slivers 24 A and 24 B that form a structure surrounding gate structure 16 . Slivers 24 A and 24 B aid in the implanting step forming source region 18 and drain region 20 . In the same implanting step extensions 22 A and 22 B are also formed. Thus, the present invention provides source region 18 , drain region 20 and their respective extensions 22 A and 22 B in one single masking step.

FIGS. 2 a - 2 j illustrates the various steps in manufacturing structure 10 of FIG. 1 . First, conventional N-doped silicon substrate 12 is provided (FIG. 2 a ). Then, as illustrated in FIG. 2 b , oxide layer 14 (e.g., 1.5-2.5 nm thick) is provided on silicon substrate 12 . Next, polysilicon layer 26 is provided in a conventional manner on oxide layer 14 (FIG. 2 c ). Polysilicon layer can be provided, for example, pre-doped with a thickness of 125-175 nm. Polysilicon layer 26 is then patterned to form gate structure 16 (FIG. 2 d ). Oxide layer 14 is also substantially removed from the areas exposed after removal of polysilicon from polysilicon layer 26 . Next, oxide layer 28 , approximately 10-15 nm thick, is formed (FIG. 2 e ) over gate structure 16 and the exposed areas. Then, nitride layer 30 is formed over the oxide layer 28 (FIG. 2 f ). Nitride layer 30 can be deposited, for example, to approximately 70-120 nm thick using a chemical vapor deposition process. Nitride layer 30 is then anisotropically etched to form spacers 32 of approximately 50-85 nm wide, as illustrated in FIG. 2 g . Then, oxide layer 34 is formed over nitride spacers 32 and oxide layer 28 atop gate structure 16 (FIG. 2 h ). A portion of oxide layer 34 and a portion of oxide layer 28 atop gate structure 16 are etched back to form slivers 36 on the outside of nitride spacers 32 . The resulting structure is illustrated in FIG. 2 i . Thus, the structure in FIG. 2 i has gate structure 16 surrounded by a channel-shaped oxide layer, with the channel filled by the material of nitride spacers 32 . Next, the nitride in nitride layers 32 is removed using hot phosphoric acid (FIG. 2 j ). Next, dopants are implanted into silicon substrate 12 to form source region 18 , drain region 20 , and extensions 22 A and 22 B, as shown in FIG. 1 .

In the implantation step forming source region 18 , drain region 20 and extensions 22 A and 22 B, dopants are implanted into silicon substrate 12 using implantation steps from four rotated positions of the wafer, and at a tilt angle of 15-30°. For a N-type implant (i.e., arsenic or phosphorus), an energy of 15-25 KeV can be used. For a P-type implant (e.g., BF 2 ), an energy of of 10-20 KeV can be used. Masked by structure 10 , extensions 22 A and 22 B receives approximately a 35-40 percent dose relative to the dose received at source region 18 and drain region 20 .

The exemplary embodiments of the invention disclosed above are illustrative and not limiting. Other embodiments of this invention are possible within the scope of the invention.