Inventor

Zoran Krivokapic

Inventor

Santa Clara, CA, US

Overview

1993–2019

Patent span

Electricity

Primary field (CPC H)

Patents· 152 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices44%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%

B82YSpecific uses or applications of nanostructures6%

H10BElectronic memory devices5%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

G11CStatic stores3%

H01LSemiconductor devices3%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%

C23CCoating metallic material1%

PatentTitleYear

10,332,969Negative capacitance matching in gate electrode structures2019 10,141,414Negative capacitance matching in gate electrode structures2018 10,002,859Fin-FET resonant body transistor2018 9,997,695Methods to utilize piezoelectric materials as gate dielectric in high frequency RBTs in an IC device2018 9,899,363'Fin-FET resonant body transistor'2018 9,685,529'III-V NFETs including channel barrier layers to reduce band-to-band leakage current'2017 9,673,376'Methods to utilize piezoelectric materials as gate dielectric in high frequency RBTs in an IC device'2017 9,663,346'MEMs-based resonant FinFET'2017 8,815,739'FinFET device with a graphene gate electrode and methods of forming same'2014 8,681,570'Methods and systems for memory devices with asymmetric switching characteristics'2014 8,605,481'Crossbar array memory elements and related read methods'2013 8,580,660'Double and triple gate MOSFET devices and methods for making same'2013 8,502,283'Strained fully depleted silicon on insulator semiconductor device'2013 8,431,466'Method of forming finned semiconductor devices with trench isolation'2013 8,368,219'Buried silicide local interconnect with sidewall spacers and method for making the same'2013 8,334,181'Germanium MOSFET devices and methods for making same'2012 8,331,135'Signal control elements in ferromagnetic logic'2012 8,304,760'Sidewall graphene devices for 3-D electronics'2012 8,222,680'Double and triple gate MOSFET devices and methods for making same'2012 8,207,757'Nonvolatile CMOS-compatible logic circuits and related operating methods'2012 8,102,000'P-channel germanium on insulator (GOI) one transistor memory cell'2012 8,049,334'Buried silicide local interconnect with sidewall spacers and method for making the same'2011 7,994,020'Method of forming finned semiconductor devices with trench isolation'2011 7,993,986'Sidewall graphene devices for 3-D electronics'2011 7,973,364'Method for forming a one-transistor memory cell and related structure'2011 7,939,247'Process of patterning small scale devices'2011 7,871,873'Method of forming fin structures using a sacrificial etch stop layer on bulk semiconductor material'2011 7,858,990'Device and process of forming device with pre-patterned trench and graphene-based device structure formed therein'2010 7,858,989'Device and process of forming device with device structure formed in trench and graphene layer formed thereover'2010 7,816,767'Negative differential resistance diode and SRAM utilizing such device'2010 7,786,003'Buried silicide local interconnect with sidewall spacers and method for making the same'2010 7,781,810'Germanium MOSFET devices and methods for making same'2010 7,670,914'Methods for fabricating multiple finger transistors'2010 7,611,935'Gate straining in a semiconductor device'2009 7,508,050'Negative differential resistance diode and SRAM utilizing such device'2009 7,402,505'Single electron devices formed by laser thermal annealing'2008 7,378,310'Method for manufacturing a memory device having a nanocrystal charge storage region'2008 7,335,594'Method for manufacturing a memory device having a nanocrystal charge storage region'2008 7,309,650'Memory device having a nanocrystal charge storage region and method'2007 7,306,997'Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor'2007 7,235,436'Method for doping structures in FinFET devices'2007 7,202,118'Fully depleted SOI MOSFET arrangement with sunken source/drain regions'2007 7,196,372'Flash memory device'2007 7,192,836'Method and system for providing halo implant to a semiconductor device with minimal impact to the junction capacitance'2007 7,179,692'Method of manufacturing a semiconductor device having a fin structure'2007 7,148,526'Germanium MOSFET devices and methods for making same'2006 7,105,425'Single electron devices formed by laser thermal annealing'2006 7,029,958'Self aligned damascene gate'2006 7,012,298'Non-volatile memory device'2006 7,001,807'Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same'2006 6,984,569'Shallow trench isolation (STI) region with high-K liner and method of formation'2006 6,975,014'Method for making an ultra thin FDSOI device with improved short-channel performance'2005 6,921,963'Narrow fin FinFET'2005 6,919,250'Multiple-gate MOS device and method for making the same'2005 6,917,068'Semiconductor device having conductive structures formed near a gate electrode'2005 6,913,959'Method of manufacturing a semiconductor device having a MESA structure'2005 6,897,527'Strained channel FinFET'2005 6,888,198'Straddled gate FDSOI device'2005 6,873,030'Metal gate electrode using silicidation and method of formation thereof'2005 6,864,164'Finfet gate formation using reverse trim of dummy gate'2005 6,861,307'Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same'2005 6,855,583'Method for forming tri-gate FinFET with mesa isolation'2005 6,842,048'Two transistor NOR device'2005 6,833,588'Semiconductor device having a U-shaped gate structure'2004 6,830,850'Interferometric lithography using reflected light from applied layers'2004 6,828,199'Monos device having buried metal silicide bit line'2004 6,815,297'Ultra-thin fully depleted SOI device and method of fabrication'2004 6,803,631'Strained channel finfet'2004 6,765,303'FinFET-based SRAM cell'2004 6,762,483'Narrow fin FinFET'2004 6,727,149'Method of making a hybrid SOI device that suppresses floating body effects'2004 6,727,546'Self-aligned triple gate silicon-on-insulator (SOI) device'2004 6,717,212'Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure'2004 6,716,684'Method of making a self-aligned triple gate silicon-on-insulator device'2004 6,716,706'Method and system for forming a long channel device'2004 6,703,304'Dual damascene process using self-assembled monolayer and spacers'2004 6,660,578'High-K dielectric having barrier layer for P-doped devices and method of fabrication'2003 6,657,276'Shallow trench isolation (STI) region with high-K liner and method of formation'2003 6,639,271'Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same'2003 6,623,803'Copper interconnect stamping'2003 6,605,843'Fully depleted SOI device with tungsten damascene contacts and method of forming same'2003 6,599,824'System for and method of forming local interconnect using microcontact printing'2003 6,599,831'Metal gate electrode using silicidation and method of formation thereof'2003 6,596,598'T-shaped gate device and method for making'2003 6,589,823'Silicon-on-insulator (SOI)electrostatic discharge (ESD) protection device with backside contact plug'2003 6,586,755'Feed-forward control of TCI doping for improving mass-production-wise statistical distribution of critical performance parameters in semiconductor devices'2003 6,579,750'Manufacturing method for fully depleted silicon on insulator semiconductor device'2003 6,566,680'Semiconductor-on-insulator (SOI) tunneling junction transistor'2003 6,567,717'Feed-forward control of TCI doping for improving mass-production-wise, statistical distribution of critical performance parameters in semiconductor devices'2003 6,555,879'SOI device with metal source/drain and method of fabrication'2003 6,544,905'Metal gate trim process by using self assembled monolayers'2003 6,541,821'SOI device with source/drain extensions and adjacent shallow pockets'2003 6,537,920'Formation of vertical transistors using block copolymer lithography'2003 6,534,399'Dual damascene process using self-assembled monolayer'2003 6,528,858'MOSFETs with differing gate dielectrics and method of formation'2003 6,512,273'Method and structure for improving hot carrier immunity for devices with very shallow junctions'2003 6,509,234'Method of fabricating an ultra-thin fully depleted SOI device with T-shaped gate'2003 6,501,135'Germanium-on-insulator (GOI) device'2002 6,501,134'Ultra thin SOI devices with improved short-channel control'2002 6,479,858'Method and apparatus for a semiconductor device with adjustable threshold voltage'2002 6,462,381'Silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device with backside contact opening'2002 6,452,229'Ultra-thin fully depleted SOI device with T-shaped gate and method of fabrication'2002 6,448,163'Method for fabricating T-shaped transistor gate'2002 6,448,161'Silicon based vertical tunneling memory cell'2002 6,448,120'Totally self-aligned transistor with tungsten gate'2002 6,440,832'Hybrid MOS and schottky gate technology'2002 6,396,108'Self-aligned double gate silicon-on-insulator (SOI) device'2002 6,380,589'Semiconductor-on-insulator (SOI) tunneling junction transistor SRAM cell'2002 6,372,563'Self-aligned SOI device with body contact and NiSi2 gate'2002 6,365,466'Dual gate process using self-assembled molecular layer'2002 6,362,061'Method to differentiate source/drain doping by using oxide slivers'2002 6,340,417'Reactor and method for ionized metal deposition'2002 6,339,244'Fully depleted silicon on insulator semiconductor device and manufacturing method therefor'2002 6,320,236'Optimization of logic gates with criss-cross implants to form asymmetric channel regions'2001 6,304,836'Worst case design parameter extraction for logic technologies'2001 6,297,111'Self-aligned channel transistor and method for making same'2001 6,296,709'Temperature ramp for vertical diffusion furnace'2001 6,294,412'Silicon based lateral tunneling memory cell'2001 6,291,832'Resonant tunneling diode latch'2001 6,255,711'Encroachless LOCOS isolation'2001 6,246,096'Totally self-aligned transistor with tungsten gate'2001 6,238,982'Multiple threshold voltage semiconductor device fabrication technology'2001 6,194,293'Channel formation after source and drain regions are formed'2001 6,180,464'Metal oxide semiconductor device with localized laterally doped channel'2001 6,153,454'Convex device with selectively doped channel'2000 6,144,063'Ultra-thin oxide for semiconductors'2000 6,127,717'Totally self-aligned transistor with polysilicon shallow trench isolation'2000 6,100,558'Semiconductor device having enhanced gate capacitance by using both high and low dielectric materials'2000 6,100,159'Quasi soi device'2000 6,091,123'Self-aligned SOI device with body contact and NiSi.sub.2 gate'2000 6,087,208'Method for increasing gate capacitance by using both high and low dielectric gate material'2000 6,080,630'Method for forming a MOS device with self-compensating V.sub.T -implants'2000 6,025,235'Short channel transistor having resistive gate extensions'2000 6,025,635'Short channel transistor having resistive gate extensions'2000 6,008,094'Optimization of logic gates with criss-cross implants to form asymmetric channel regions'1999 5,981,358'Encroachless LOCOS isolation'1999 5,966,527'Apparatus, article of manufacture, method and system for simulating a mass-produced semiconductor device behavior'1999 5,963,824'Method of making a semiconductor device with adjustable threshold voltage'1999 5,960,291'Asymmetric channel transistor and method for making same'1999 5,928,813'Attenuated phase shift mask'1999 5,888,873'Method of manufacturing short channel MOS devices'1999 5,879,998'Adaptively controlled, self-aligned, short channel device and method for manufacturing same'1999 5,824,587'Method for making convex device with elevated gate structure'1998 5,655,110'Method for setting and adjusting process parameters to maintain acceptable critical dimensions across each die of mass-produced semiconductor wafers'1997 5,646,870'Method for setting and adjusting process parameters to maintain acceptable critical dimensions across each die of mass-produced semiconductor wafers'1997 5,643,428'Multiple tier collimator system for enhanced step coverage and uniformity'1997 5,601,954'Attenuated phase shift mask comprising phase shifting layer with parabolically shaped sidewalls'1997 5,580,428'PVD sputter system having nonplanar target configuration and methods for constructing same'1996 5,571,738'Method of making poly LDD self-aligned channel transistors'1996 5,559,357'Poly LDD self-aligned channel transistors'1996 5,556,525'PVD sputter system having nonplanar target configuration and methods for operating same'1996 5,212,106'Optimizing doping control in short channel MOS'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2013Patents assigned to ADVANCED MICRO DEVICES INC (129)· patent assignee history

1993Based in Sunnyvale, CA, US· patent location history

1996–2019Based in Santa Clara, CA, US· patent location history

2007–2013Patents assigned to SPANSION LLC (6)· patent assignee history

2010–2019Patents assigned to GLOBALFOUNDRIES INC (19)· patent assignee history

2012–2014Patents assigned to KRIVOKAPIC ZORAN (13)· patent assignee history

2012–2014Patents assigned to CHEN AN (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	129	1993–2013
GLOBALFOUNDRIES INC	19	2010–2019
KRIVOKAPIC ZORANself	13	2012–2014
SPANSION LLC	6	2007–2013
CHEN AN	5	2012–2014

Locations

Location	Patents	Span
Santa Clara, California, US	151	1996–2019
Sunnyvale, California, US	1	1993