Hybrid IGBT and MOSFET for zero current at zero voltage

This invention relates to MOSgated transistors and more specifically relates to a hybrid transistor consisting of the parallel connection of an IGBT and a power MOSFET.

MOSgated transistors such as power MOSFETs and Insulated Gate Bipolar Transistors (IGBTs) are well known and have numerous advantages over conventional junction type bipolar transistors, including a simpler drive circuit. However, in certain applications, for example, for the drive of a CRT or TV deflection coil, a high voltage MOSFET has too high an on-resistance, while an IGBT forward conduction characteristic does not provide the necessary linearity near zero voltage and zero current.

It would be desirable to provide a MoSgated device for use in high voltage (for example, 1,500 volts) circuits and which exhibit good linear behavior at low voltage and low current.

In accordance with the invention, a parallel connected power MOSFET and IGBT are used to define a high voltage MOSgated transistor which will have the low forward voltage drop of the IGBT and the linearity of the MOSFET at low voltage whereby the device can be used in place of a bipolar transistor in a TV deflection coil drive circuit or the like.

The novel device can be implemented by a copacked IGBT and power MOSFET die in a common package, as in the manner of the Schottky diode and MOSFET die in U.S. Pat. No. 5,814,884; or the MOSFET and IGBT can be integrated into a common die. In either case, the total MOSFET area is preferably about 50% that of the IGBT area and can range from 10% to 100%.

In a preferred integrated embodiment of the invention, a conventional D-MOS structure is formed on the top surface of an N − silicon die. The D-MOS structure spaced bases are then aligned vertically with alternate N + MOSFET contact regions and P + IGBT collector regions. The N + contact regions and P + collector regions are preferably spaced by about a 1 minority carrier diffusion length. These regions may be activated as by a laser anneal. A single bottom contact, preferably aluminum, then contacts the bottom regions to complete the integrated device.

FIG. 1 is a circuit diagram of the device of the invention and schematically illustrates copacked die.

FIG. 2 shows the forward voltage and forward current characteristics of the devices of FIG. 1 .

FIG. 3 is a cross-section of a small portion of the active area of an integrated MOSFET and IGBT in accordance with the invention.

Referring first to FIG. 1, there is shown a copacked MOSFET die 10 and an IGBT die 11 both mounted on a common lead frame support 12 , schematically shown in dotted lines. The die and suitable bond wires to lead frame pins are then housed by a transfer molded housing 13 in the manner shown in U.S. Pat. No. 5,814,884.

Leads or pins 15 , 16 and 17 extend from housing 13 and correspond to the source, drain and gate lead respectively for MOSFET 10 , and emitter, collector and gate respectively for IGBT 11 .

Preferably, the MOSFET die 10 will have an area of 10 to 100% of that of IGBT die 11 .

The forward voltage characteristics of the components of FIG. 1 are shown in FIG. 2 . At low forward voltage, the MOSFET 10 linear characteristics predominate, as shown in dotted line 30 . However, at higher forward current, the IGBT 11 low forward voltage drop characteristics (in solid line) will predominate. the circuit of FIG. 1 is operable in circuits which are presently served only by bipolar transistors.

FIG. 3 shows an embodiment of the invention in which the MOSFET 10 and IGBT 11 of FIG. 1 are integrated into a common die. Thus, in FIG. 3, an N − die 40 , which may be a float zone silicon die, has a top surface which contains a D-MOS type structure in its active area. Thus, a plurality of P-diffusions 41 , 42 , 43 and 44 which have conventional centrally deep P + diffusions. Each of bases 41 to 44 may be identical and may have a polygonal cellular, or parallel stripe geometry. The bases may also have different areas from one another or different shapes, if desired. Each bases 41 to 44 receive N + source diffusions 45 to 48 respectively to define invertible P-channel regions which are covered by gate oxide segments 50 to 53 which are, in turn, covered by conductive polysilicon gate segments 54 to 57 respectively.

The polysilicon gate segments, which are parts of a polygonal mesh if the bases are cellular, or are stripes if the bases are stripes, are then covered by low temperature oxide (LTO) segments 58 to 61 respectively, which are in turn covered by a top aluminum electrode 70 which will be the emitter/source electrode of the device.

After completing the top structure the die (or wafer in which it resides) is ground down to 200 to 300 microns thick, depending on the voltage rating of the device. The bottom surface of die 40 receives N + diffusions 80 and 81 which are in vertical alignment with respective 41 and 43 , thus defining N + contact regions for vertical conduction MOSFET elements of the integrated structure. P + regions 82 and 83 are next diffused into the bottom of wafer 40 and in alignment with bases 42 and 44 respectively, to act as the emitter regions of IGBT elements.

The regions 80 to 84 are spaced from adjacent regions by about 1 minority carrier diffusion length (about 50-100 microns).

The regions 80 to 84 may be activated by a laser anneal or the like.

A back contact 90 , which may be aluminum covered by other contact metals may then be formed on the bottom surface to act as the drain/collector contact of the integrated device.

Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.