Comparable circuits for parallel testing DRAM device

1. Field of the Invention

The present invention relates to a comparable circuit for testing DRAM devices, and more particularly, to a comparable circuit for parallel testing the DRAM devices with self-diagnostic mechanism.

2. Description of the Prior Art

The approaches of the memory devices bring the modern electrical devices broadly employed in human' lives because the kernels of the electrical devices, which are usually the microprocessors and microcomputers, store or retrieve their currently used data from memories on-chip therein. Those commonly used memory devices, especially DRAM (dynamic random access memory) devices, are broadly used memories due to their cost and operation speeds. In the present days, a high density DRAM device having 2 20 bits or more has been developed in an integrated circuit. A testing procedure is thus unavoidable especially when the DRAM devices are mass-produced.

Nowadays, parallel testing becomes a common used approach for testing whether a DRAM device is fault because many DRAM devices can be detected simultaneously. Please refer to FIG. 1, which depicts a 4M×4 DRAM device 100 composed of four 1M×4 memory cells 100 A, 100 B, 100 C, and 100 D to be parallel detected in U.S. Pat. No. 4,860,259 disclosed by Tobita. I/O bus having four testing signals IO 0 , IO 1 , IO 2 , IO 3 , are routed into the detected cells 100 A to 100 D simultaneously but accompanied with a control signal S test for indicating the testing period. For example, S test can be pulled to high (logic 1) under a WCBR (Write CAS (Column Address Strobe) Before RAS (Row Address Strobe)) specification and accompanied with a test pattern loaded on IO 0 , IO 1 , IO 2 , and IO 3 . Four I/O blocks (IOBLK) 102 A, 102 B, 102 C, and 102 D latch the loaded test pattern and direct it to cells 100 A, 100 B, 100 C, and 100 D for storing when selection signals SECA, SECB, SECC, and SECD are enabled, respectively. Next, the stored test pattern is read from cells 100 A, 100 B, 100 C, and 100 D and then routed to a associated comparable circuit for detecting whether the test pattern is written correctly. Each one of the comparable circuits 104 A, 104 B, 104 C, and 104 D consists of two exclusive OR (XOR) gates 106 and 108 , an OR gate 110 and a tri-state output buffer 112 to generate a one bit output by using the test pattern. The one bit output is then respectively routed on IO 0 , IO 1 , IO 2 , and IO 3 according to their sections. Accordingly, by detecting the logic states from IO 0 , IO 1 , IO 2 , and IO 3 can decide whether the detected memory cell is defective or not. For example, if a test pattern {0000} that is stored in then read out from the memory cell 100 A, both outputs of the XOR gates are logic 0 because all their input terminals receive logic 0 as inputs. Obviously, the outputs of both the OR gate 110 and output buffer 112 are logic 0, which indicates the detected memory cell is perfect. In contrast, if logic 1 appears on the output buffer, the detected memory cell can be concluded as defective because an error evidently occurs when retrieving the stored test pattern. As noted, logic 1 and logic 0 appear on I/O bus indicate an error or a normal condition is obtained in the testing procedure according to WCBR specification. One disadvantage of the Tobita reference is that only four test patterns {0000}, {0011}, {1100} and {1111} can be used in the comparable circuit. Any test pattern having different logic states at two input terminals of the XOR gates 106 or 108 will cause the output buffer 112 to output logic 1, the detected memory cell is thus treated as defective even it is perfect. Additional test procedures are thus unavoidable for testing DRAM devices.

Another conventional approach, such as the circuits disclosed by McClure et al in U.S. Pat. No. 5,265,100 is also shown in FIG. 2 for testing the DRAM devices. In McClure reference, four comparable circuits 204 A, 204 B, 204 C and 204 D are provided for detecting the retrieved test patterns from the memory cells 100 A, 100 B, 100 C and 100 D, respectively. Each one of the comparable circuits 204 A, 204 B, 204 C and 204 D is composed of two exclusive NOR (XNOR) gates 206 and 208 , a NADN gate 210 , and a tri-state output buffer 212 . Operations of the McClure reference are similar to Tobita reference except the comparable circuits are. For example, a testing pattern is also loaded on IO 0 , IO 1 , IO 2 , and IO 3 , and directed into the detected devices 100 A to 100 D simultaneously, a control signal S test is also accompanied with to indicate the testing period. Four one bit outputs of the output buffers 212 are also respectively routed on IO 0 , IO 1 , IO 2 , and IO 3 according to their sections. However, only four test patterns as the Tobita reference's can be used in McClure reference because any test pattern having different logic states at two input terminals of the XNOR gates 206 or 208 will cause the output buffer 212 to be logic 1. Additional test procedures are also unavoidable because the detected memory cell will also be treated as defective even it is perfect. On the other hand, another fatal disadvantage of the above two references is that it is impossible to distinguish whether a detected memory cell is defective when the comparable circuit is imperfect. Please refer to FIG. 4A, which depicts a short circuit 214 occurs between two input terminals (nodes E and F) of the NAND gate 210 . Obviously, nodes E and F always keep the same logic state due to the short circuit 214 whatever the logic states of nodes A, B, C, and D are. Therefore, the logic state of node G (also the input terminal of the output buffer 212 ) can not correctly indicate the currently detecting situation. A need has arisen to disclose a comparable circuit, in which the disadvantages of the conventional schemes, such as fewer test patterns can be employed and it is impossible to distinguish whether the comparable circuit or the detected memory cell is defective, can be completely overcome.

The principal object of the invention is to provide a comparable circuit for parallel detecting DRAM devices with more test patterns.

The other object of the invention is to provide a comparable circuit with self-diagnostic mechanism.

According to the aforementioned objects, the disclosed comparable circuit basically includes a three-stage circuit composed of two XNOR gates, a XOR gate, and a tri-state output buffer. The first stage consisting of the XOR gate and a first XNOR gate parallel receive the stored test pattern from the detected memory cell to respectively generate the first comparison results. A second exclusive XNOR gate included in the second stage receives the comparison results from the first stage as inputs, and connects with the third stage through an output terminal of the second XNOR gate. The third stage composed of the output buffer couples with the output terminal of the second XNOR gate to generate the second comparison result routed on I/O bus. Chess-like test patterns can be employed in the disclosed comparable circuit due to two mutually exclusive logic gates are applied in the first stage. On the other hand, logic 1 freezes on I/O bus if two input terminals of the second XNOR gate are shorted, which indicates the comparable circuit is defective.

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjuntion with the accompanying drawings, wherein:

FIG. 1 depicts a 4M×4 DRAM device composed of four 1M×4 memory cells to be parallel detected in Tobita reference;

FIG. 2 depicts a 4M×4 DRAM device composed of four 1M×4 memory cells to be parallel detected in McClure reference;

FIG. 3 depicts the comparable circuit disclosed in the present invention;

FIG. 4A depicts a short circuit occurs between two input terminals of the second stage in Tobita reference; and

FIG. 4B depicts a short circuit occurs between two input terminals of the second stage in the invention.

Please refer to FIG. 3, which demonstrates a schematic diagram illustrative of the circuit diagram of the invention, wherein four comparable circuits 304 A, 304 B, 304 C, and 304 D are shown therein. Each the comparable circuit is composed of two XNOR gates 306 and 310 , a XOR gate 308 , and a tri-state output buffer 312 . Furthermore, each the comparable circuit can be divided into a three-stage circuit as descriptions given hereinafter. The first stage consisting of the XOR gate 308 and a first XNOR gate 306 parallel receive the stored test pattern from the detected memory cell to generate first comparison results. Please note that the first comparison results are a pair of outputs from output terminals of the XNOR gate 306 and NOR gate 308 , and identical test results will be obtained even exchanging the positions between the XNOR gate 306 and the NOR gate 308 in first stage. A second XNOR gate 310 included in the second stage receives the first comparison results from the first stage and connects with the third stage through an output terminal of the second XNOR gate 310 . As noted, the second comparison result generated by the second XNOR gate 310 are directed from an output terminal of the XNOR gate 310 to the third stage. The third stage composed of the output buffer 312 couples with output terminal of the second XNOR gate 310 to receive the second comparison result, wherein the second comparison result is directed to I/O bus according to the control signal S test .

Test operations employed in the invention are the same as the aforementioned conventional approaches. For example, a testing pattern is also loaded on I/O bus (i.e., IO 0 , IO 1 , IO 2 , and IO 3 ) and directed into the detected devices 100 A to 100 D simultaneously, and further accompanied with a control signal S test for indicating the testing period by following WCBR specification. Four one bit outputs of the output buffers 312 are also respectively routed on I/O bus according to their sections. However, four more chess-like test patterns {0101}, {1010}, {1001}, and {0110} can be applied in the disclosed comparable circuit due to XOR and XNOR gates are employed. By using the test pattern {0101} as example, logic 0 and logic 1 respectively appear at output terminals of the first XNOR gate 306 and NOR gate 308 . Accordingly, logic 0 will simultaneously appear on output terminals of both the second XNOR gate 310 and the output buffer 312 . It is noted that the outputs of the first XNOR gate 306 and XOR gate 308 are mutually inverted phase to each other, and the detected logic 0 is directed on I/O only when the control signal S test is enabled. Of course, the other three chess-like test patterns significantly have the same test results as the test pattern {0101}. DRAM devices can thus be parallel tested by means of four more test patterns than before.

On the other hand, the disclosed comparable circuit will maintain (or fixed) at logic 1 at which the comparable circuit is defective. For example, please refer to FIG. 4B, which depicts a short circuit 314 occurs between nodes E′ and F′ (i.e., two input terminals of XNOR gate 310 ) of the second stage in the invention. Logic 1 freezes on node G′ evidently when a short circuit occurs between two input terminals of the second XNOR gate 310 no matter what the voltage levels of the nodes A′, B′, C′ and D′ are. The operators can immediately know which one of the comparable circuits is imperfect by conclusion from testing some memory cells.

Elementary advantages offered by the disclosed comparable circuit are described following. Firstly, four more chess-like test patterns can be normally employed for testing DRAM devices, which indicates that more defective DRAM devices can be detected and then removed when a parallel testing procedure is performed. Secondly, a self-diagnostic mechanism is included therein for indicating a short circuit occurs inside the comparable circuit. The operators can replace another perfect comparable circuit for continuing consequent test procedures instead of testing the DRAM devices without consciousness.

As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrated of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, such as exchanging the positions of the XNOR and XOR gates, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.