Inventor
Yung-Fa Chou
Inventor
Kaohsiung, TW
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1029%
G11CStatic stores24%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
G01RMeasuring electric variables9%
H01LSemiconductor devices9%
H03KPulse technique6%
G05FSystems for regulating electric or magnetic variables3%
Y10TTechnical subjects covered by former us classification3%
PatentTitleYear
9,347,981'Test method for interposer'20169,064,549'Memory device'20159,048,342'Semiconductor device stacked structure'20158,937,486'Method for testing through-silicon-via'20158,912,015'Operating method of hardwired switch'20148,854,853'Technology of memory repair after stacking of three-dimensional integrated circuit'20148,710,676'Stacked structure and stacked method for three-dimensional chip'20148,683,276'Apparatus and method for repairing an integrated circuit'20148,531,199'Method for testing through-silicon-via and the circuit thereof'20138,384,201'Wafer and method for improving yield rate of wafer'20138,344,520'Stacked structure of chips'20138,217,521'Hardwired switch of die stack and operating method of hardwired switch'20128,193,006'Method of chip repair by stacking a plurality of bad dies'20128,026,585'Die stacking structure and fabricating method thereof'20117,924,083'Isolation circuit'20116,591,384'Comparable circuits for parallel testing DRAM device'20036,396,731'SRAM cell employing tunnel switched diode'20026,236,598'Clamping circuit for cell plate in DRAM'20016,204,576'High-voltage switch circuit'20016,201,435'Low-power start-up circuit for a reference voltage generator'20016,060,925'Schmitt-trigger circuit with low power consumption'20005,909,394'Precharge circuit for preventing invalid output pulses caused by current sensing circuits in flash memory devices'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2003Patents assigned to TAIWAN SEMICONDUCTOR MFG (7)· patent assignee history
1999Based in Hsinchu, TW· patent location history
2000–2016Based in Kaohsiung, TW· patent location history
2011–2016Patents assigned to IND TECH RES INST (13)· patent assignee history
2012–2015Patents assigned to CHOU YUNG-FA (9)· patent assignee history
2012–2015Patents assigned to KWAI DING-MING (9)· patent assignee history
2012–2014Patents assigned to CHEN TING-SHENG (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IND TECH RES INST | 13 | 2011–2016 |
| CHOU YUNG-FAself | 9 | 2012–2015 |
| KWAI DING-MING | 9 | 2012–2015 |
| TAIWAN SEMICONDUCTOR MFG | 7 | 1999–2003 |
| CHEN TING-SHENG | 3 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kaohsiung, TW | 21 | 2000–2016 |
| Hsinchu, TW | 1 | 1999 |