Priority determining circuit for non-volatile memory

The present invention relates to a priority determining circuit for a non-volatile memory formed by at least two memory banks.

More particularly, the invention relates to a priority determining circuit for non-volatile memory which controls the functional development of the memory banks that constitute the memory, ensuring their correct operation and determining, in each individual instance, interdependent priorities and synchronizations.

It is known that a non-volatile memory generally comprises a single array which is addressed from outside and is univocally associated with a read mode which allows to extract from it the information item at the chosen memory location.

Such a memory requires no particular sub-block management, since it only has to perform controls and optimizations of internal propagations of the signals.

Clearly, this architecture is preferred when no particular speed performance is required: its simplicity and compact size are the foundations of its stability.

However, when a memory is required to have extreme speed, the above solution is not satisfactory; accordingly, more complex and innovative design approaches have been devised, such as page-mode reading, parallel reading, and the so-called interleaved architecture.

In the field of extremely fast memory architectures, memories of the interleaved type are particularly important. These memories, which assume long sequences of sequential read operations, are organized so as to start two read processes which are parallel as regards the propagation complementarity characteristics and the activity of the memory.

In this manner, the two fundamental steps of a read cycle (pre-charge and evaluation) occur together between the two read processes, with a temporally “interleaved” mode.

In order to provide a memory with the above-described characteristics it is necessary to organize the array, the corresponding structures indirectly and the read circuits into two identical and distinct but independent banks. Accordingly, it is evident that there is a need to provide control and synchronization between the two perfectly identical banks in the memory which must be implemented and provided even in the absence of external pointers.

The aim of the present invention is to provide a priority determining circuit for a non-volatile memory which allows to manage the evolution of two parallel read streams in a memory, controlling its functional evolution.

Within the scope of this aim, an object of the present invention is to provide a priority determining circuit for non-volatile memories which allows to manage the evolution of the two read streams, determining which of the two banks of the memory must be set to evaluation mode and which one must be set to pre-charge mode and which one must be updated in its affected location and which one must not be updated.

Another object of the present invention is to provide a priority determining circuit for non-volatile memories which allows to suspend the interleaved mode of the memory, allowing reading with exclusively external addressings.

Another object of the present invention is to provide a priority determining circuit for non-volatile memories which allows to preset separate time intervals for updating activities between the read paths of each memory bank and the counters.

Another object of the present invention is to provide a priority determining circuit for a non-volatile memory which is highly stable, relatively easy to provide and at competitive costs.

This aim, these objects and others which will become apparent hereinafter are achieved by a priority determining circuit for a non-volatile memory formed by at least one pair of memory banks, each bank having a counter, characterized in that it comprises:

means for latching a read address of said memory;

master latch means for said address;

slave latch means for said address;

pointer means for read paths of the memory bank to be read of said memory, stimulated by said master latch means;

means for enabling a path for connecting said master latch means and said slave latch means;

means for enabling a path for connecting said slave latch means and said master latch means;

means for managing the increment of said counters which are connected to said slave latch means;

said read address of said memory being loaded by said master latch means into said slave latch means and then by said slave latch means into said master latch means alternately, said master latch means synchronizing timer means of said memory which are meant to activate sense amplifiers of said memory and said slave latch means driving said means for managing the increment of said counters, for an advancement of the read cycle of said memory.

Further characteristics and advantages of the invention will become apparent from the description of a preferred but not exclusive embodiment of the priority determining circuit according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein:

FIG. 1 is a block diagram of the priority determining circuit according to the present invention;

FIG. 2 is a circuit diagram of the priority determining circuit according to the present invention;

FIG. 3 is a block diagram of the timing management circuit used in combination in the priority management circuit according to the present invention;

FIG. 4 is a circuit diagram of the read determining circuit of one of two master and slave latches of the priority determining circuit according to the invention;

FIG. 5 is a block diagram of the memory architecture in which the priority determining circuit according to the present invention is inserted; and

FIG. 6 is a waveform diagram illustrating an operation of the block diagram of the memory architecture shown in FIG. 5 .

With reference to the above-cited figures, and initially to FIG. 1, the priority determining circuit according to the present invention comprises address latching means 1 , constituted by a latch, which are suitable to store an address 2 that originates from outside the memory and passes through a structure 3 of the tristate type which is driven by a signal ALE-fast which allows to enable the passage of the address 2 in the latch means 1 .

The output of the latch means 1 is fed to master latch means 4 which are conveniently constituted by a latch and the passage of the data from the latch means 1 to the latch means 4 is driven by a pass transistor, which is enabled by a signal ALE which indicates address latch enabling.

The master latch means are in turn connected, by means of a suitable path, to slave latch means 5 which allow to store, when suitable conditions occur, the contents of the master latch means 4 .

The path that connects the master latch means 4 to the slave latch means 5 is formed by means for pointing read paths of the memory bank, designated by the reference numeral 6 , with the particularity of adding or not inversions on said path, depending on the state of a signal BURST, which indicates the reading of said memory in sequential mode. The pointer means are directly connected to the master latch means 4 and are in turn connected to means for enabling the connection between the master latch means and the slave latch means, designated by the reference numeral 7 .

The slave latch means 5 are connected, by means of signals PR-INC-OD and PRI-INC-EV, to means 8 for managing the increment to be assigned to the counters of the two memory banks, which emit in output a signal INC-OD for incrementing the odd memory bank and a signal INC-EV for incrementing the even memory bank, receiving in input the increment signal INC.

Said increment signal is generated by the means for determining the increment INC 9 , which are the subject of a co-pending patent application in the name of this same Applicant and emit in output a signal INC and a signal PRI-INC for synchronization, which indicates which memory bank is to be read, and said signal PRI-INC is fed to means 10 for generating signals for enabling the path for connection between the master latch means 4 and the slave latch means 5 .

Said connection enabling signals are the signals M-RD and S-RD for enabling, respectively, the connection between the master latch means 4 and the slave latch means 5 and between the slave latch means 5 and the master latch means 4 .

The signal M-RD is used to enable the enabling means 7 , while the signal S-RD is used to enable enabling means 11 which allow connection between the slave latch means 5 and the master latch means 4 .

In detail, connection enabling means, designated by the reference numeral 12 and driven by the signal ALE, are present between the latch means 1 and the master latch means 4 .

The signal in output from the master latch means 4 is the signal designated by PRI-EV, which further passes into inverting means 13 for generating the signal PRI-OD.

The signals PRI-EV and PRI-OD for indicating the memory bank to be read are fed to the read path pointer means of the memory bank to be read 6 , whose switching is determined by the signal BURST, for continuous reading of the memory.

FIG. 2 is a circuit diagram that corresponds to the block diagram of FIG. 1 . Said diagram is to be considered purely as an example, since the block diagram of FIG. 1 may be provided by using different but functionally similar circuit diagrams.

FIG. 3 illustrates a logic circuit which shows the generation of signals EV-EQ, OD-EQ for controlling sense amplification, and signals EV-OK, OD-OK for controlling the odd and even memory banks, respectively.

Said logic circuit has NAND gates 15 , 16 , 17 and 18 which receive in input, for the gates 15 and 16 , the signals PRI-OD (odd bank priority), EQ-SYNC (equalization synchronization) and PRI-EV (even memory bank priority), while the gates 17 and 18 receive in input the signal OK-SYNC, in order to generate the memory bank control signals.

FIG. 4 illustrates a logic circuit for generating the increment signals M-INC and S-INC for the master latch means 4 and the slave latch means 5 , respectively.

The circuit of FIG. 4 is a formed by a NOR gate 19 which receives in input the signal PRI-INC at one input, said signal being also sent to a NAND gate 20 . The output of the NOR gate 19 is the signal M-INC, which is fed to an inverter 21 and from there is fed, as second input M-INC, to the NAND gate 20 .

The output of the NAND gate 20 is a signal S-INCn which is fed to a second inverter 22 whose output of the signal S-INC also constitutes the second input of the NOR gate 19 .

FIG. 5 illustrates an architecture of a memory with the priority determining circuit according to the invention, which is designated by the reference numeral 100 . In this architecture, the reference numeral 101 designates an even memory array block, while the reference numeral 102 designates an odd memory array block. The reference numeral 103 designates a counter for the memory block 101 and the reference numeral 104 designates a counter which is similar to the counter 103 for the memory block 102 .

Each memory block also has a respective sense amplifier 105 and 106 which is connected in output to a structure of the tristate type 107 and 108 from which the data in output from the sense amplifier are output.

A timing management unit 110 manages the pre-charge/evaluation steps of the amplifier means 105 and 106 by means of the control signals EV-EQ and OD-EQ and further controls the driving of the structures of the tristate type 107 and 108 which are meant to update the output information item by means of the signals EV-EQ, OD-EQ and EV-OK, OD-OK. Said timing management unit 110 is shown in detail in FIG. 3 .

The reference numeral 9 instead designates the increment determining means, already shown in FIG. 1 . Finally, the reference numeral 111 designates a control block which is interfaced between the priority determining circuit 100 according to the present invention and the increment determining means 9 .

With reference to the above figures, and furthermore with reference to FIG. 6, which illustrates the timing of the various signals of the device, operation of the circuit according to the invention is as follows.

Two operating modes of the memory can be distinguished:

conventional mode (signal ALE=1 at all times)

interleaved or burst mode (signal ALE is pulsed, first “1” and then “0”).

As regards the conventional mode, when the signal “ALE” is set and kept at “1”, the external address configures and maintains the master latch means 4 and the slave latch means 5 . In this way, the two pairs of signals PRI-EV, PRI-OD and INC-EV, INC-OD are set appropriately from outside.

Moreover, in this situation the signal BURST is at a low level (0), acting on the means for switching the read path of the memory, so as to select a path which provides an “even” number of inversions in the loop which is formed by the master latch means 4 and by the slave latch means 5 and is closed on the master latch means 4 .

Said loop is interrupted at the level of the connection between the slave latch means 5 and the master latch means 4 by means of the pass gate 11 controlled by the signal S-RD, while the path between the master latch means 4 and the slave latch means 5 is kept continuously connected by the pass gate 7 controlled by the signal M-RD.

Since no synchronization pulse PRI-INC is possible in this configuration, the configuration of the circuit therefore does not change over time and therefore the pointing signals PRI-EV, PRI-OD and INC-EV, INC-OD are controlled directly from outside the memory.

As regards the interleaved or burst mode, it is always set starting from an initial conventional operating mode by means of the pulsed signal ALE (which is then kept at the low level 0), so that during the first cycle (which lasts from the pulse of ALE to the occurrence, generated inside the memory, of the high BURST signal “1”), the operation of the circuit is the same as in the above-described conventional mode.

When the signal BURST=1 occurs (and persists throughout the period of validity of the BURST mode, ALE=0) an additional inversion (selection of the output of the inverter 13 instead of its input) is introduced in the structure 6 of FIG. 2 (by means of the action of BURST) in the loop formed by the master 4 , the slave 5 and the master 4 , so that since said inversion is odd, at each event of the pulse PRI-INC the circuit modifies its configuration, thus updating the pointing of the banks PRI-EV, PRI-OD, and of the counters INC-OD, INC-EV. All this occurs in an alternating succession.

The primary signals PRI-EV and PRI-OD allow to control in an orderly fashion the pairs EV-EQ, OD-EQ and EV-OK, OD-OK.

It is important to note (see FIG. 6) that the updating of the controls related to the read paths occurs at the beginning of the update pulses PRI-INC and simultaneously with the generation of the pulse INC-EV or INC-OD, while the signals meant to update the increment PRI-INC-OD occur at the end, and only at the end, of the update pulse PRI-INC.

This is devised in order to prevent “chasing” phenomena and oscillations in the system.

It is also important to consider the fact that access from outside to the update circuit is performed by means of a filter network so as to prevent false requests for configuration from outside, which are often induced by noise.

The signals that arrive from the priority circuit (PRI-EV and PRI-OD) are then combined with the synchronization signal EQ-SYNC in a synchronous and complementary manner (when SYNC is activated) with respect to the pre-charge/evaluation activities of the two memory banks. Likewise, the same priority signals, combined with an additional synchronization signal OK-SYNC, enable the data transfer, in an exclusive mode, from the read circuits to the output structures by virtue of the activation of one of the two enable signals EV-OK or OD-OK.

Dually, a suitable synchronization signal INC, under the control of the priority increment signals PRI-INC-OD and PRI-INC-EV, selects the activation of one of the two signals INC-OD and INC-EV, thus causing the increment of the corresponding associated counter and only of that counter.

Attention is also drawn to the characteristic of the priority updating control network, which by being stimulated by the synchronization pulses PRI-INC produces signals in pairs which do not mutually overlap for controlling the connection between the master part and the slave part.