Inventor
Luigi Pascucci
Inventor
Sesto San Giovanni, IT
Overview
Patents· 153 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores73%
H03KPulse technique6%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems5%
Y10TTechnical subjects covered by former us classification4%
G05FSystems for regulating electric or magnetic variables3%
H10BElectronic memory devices2%
H10DInorganic electric semiconductor devices2%
G06FElectric digital data processing1%
H03MCoding1%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%
PatentTitleYear
10,825,524Memory device with a common source select line for two memory portions of a logic sector202010,825,525Programming non-volatile electronic memory device with NAND architecture202010,170,191Electronic memory device having two portions that can be decoupled20199,287,284'Semiconductor field-effect transistor, memory cell and memory device'20168,824,205'Non-volatile electronic memory device with NAND structure being monolithically integrated on semiconductor'20148,759,915'Semiconductor field-effect transistor, memory cell and memory device'20148,630,115'Non-volatile electronic memory device with NAND structure being monolithically integrated on semiconductor'20148,030,765'Configuration terminal for integrated devices and method for configuring an integrated device'20117,649,778'Method for accessing in reading, writing and programming to a NAND non-volatile memory electronic device monolithically integrated on semiconductor'20107,529,881'Method for accessing in reading, writing and programming to a nand non-volatile memory electronic device monolithically integrated on semiconductor'20097,525,851'Row decoder circuit and related system and method'20097,501,705'Configuration terminal for integrated devices and method for configuring an integrated device'20097,417,900'Method and system for refreshing a memory device during reading thereof'20087,397,700'Non-volatile memory electronic device with NAND structure being monolithically integrated on semiconductor'20087,397,702'Read/verify circuit for multilevel memory cells with ramp read voltage, and read/verify method thereof'20087,295,472'Integrated electronic non-volatile memory device having nand structure'20077,274,594'Non-volatile memory electronic device with NAND structure being monolithically integrated on semiconductor'20077,181,592'Pointer circuit'20077,031,189'Non-volatile latch circuit'20067,023,728'Semiconductor memory system including selection transistors'20067,016,931'Binary-number comparator'20066,967,876'Method for controlling programming voltage levels of non-volatile memory cells, the method tracking the cell features, and corresponding voltage regulator'20056,958,510'Process for fabricating a dual charge storage location memory cell'20056,930,927'Line selector for a matrix of memory elements'20056,920,066'Programming method of the memory cells in a multilevel non-volatile memory device'20056,882,001'Electrically-programmable non-volatile memory cell'20056,826,083'Method for reducing spurious erasing during programming of a nonvolatile NROM'20046,804,756'Synchronization circuit for read paths of an electronic memory'20046,701,419'Interlaced memory device with random or sequential access'20046,700,819'Memory with improved differential reading system'20046,696,990'Binary encoding circuit'20046,594,180'Semiconductor memory system'20036,587,913'Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode'20036,580,637'Semiconductor memory architecture'20036,552,952'Column multiplexer for semiconductor memories'20036,549,485'Control and timing structure for a memory'20036,525,591'Circuit for selectively enabling one among a plurality of circuit alternatives of an integrated circuit'20036,501,700'Internal addressing structure of a semiconductor memory'20026,477,625'Method and system for reading a memory by applying control signals thereto'20026,438,669'Timesharing internal bus, particularly for non-volatile memories'20026,438,040'Enabling circuit for output devices in electronic memories'20026,424,575'Synchronous output buffer, particularly for non-volatile memories'20026,373,781'Priority determining circuit for non-volatile memory'20026,362,658'Decoder for memories having optimized configuration'20026,356,505'Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and related circuit'20026,351,434'Synchronous counter for electronic memories'20026,330,188'Data read circuit for non volatile memory cells'20016,324,238'Bit counter stage, particularly for memories'20016,320,440'Method for selectively enabling alternative circuits'20016,275,416'Pulse generator circuit, particularly for non-volatile memories'20016,249,463'Address latch enable signal control circuit for electronic memories'20016,212,128'Address transition detector in semiconductor memories'20016,212,096'Data reading path management architecture for a memory device, particularly for non-volatile memories'20016,195,286'Circuit and method for reading a non-volatile memory'20016,175,521'Voltage regulator for programming electrically programmable non-volatile memory cells in a cell matrix'20016,148,413'Memory under test programming and reading device'20006,100,740'Circuit for selectively enabling one among a plurality of circuit alternatives of an integrated circuit'20006,081,911'Method and circuit architecture for testing a non-volatile memory device'20006,078,523'Gain modulated sense amplifier and method of operating the same'20006,061,273'Pre-charge step determining circuit of a generic bit line, particularly for non-volatile memories'20006,046,619'Asymmetrical pulsive delay network'2000RE036579'Sense circuit for reading data stored in nonvolatile memory cells'20005,986,954'Self-regulated equalizer, particularly for sense amplifiers'19995,968,183'Semiconductor memory device with clocked column redundancy and time-shared redundancy data transfer approach'19995,959,917'Circuit for detecting the coincidence between a binary information unit stored therein and an external datum'19995,959,935'Synchronization signal generation circuit and method'19995,959,476'Circuit and method for generating a power-on reset signal'19995,946,237'Nonvolatile memory device capable of reading data with a reduced number of word lines'19995,936,907'Method for detecting redunded defective addresses in a memory device with redundancy'19995,917,768'Memory architecture for flexible reading management, particularly for non-volatile memories, having noise-immunity features, matching device performance, and having optimized throughout'19995,914,867'Voltage generator-booster for supplying a pulsating voltage having approximately constant voltage levels'19995,914,901'Integrated circuit for generating initialization signals for memory cell sensing circuits'19995,905,678'Control circuit of an output buffer'19995,903,166'Circuit for immunizing an integrated circuit from noise affecting enable signals of the integrated circuit'19995,901,087'Gain modulated sense amplifier'19995,889,710'Semiconductor memory device with row redundancy'19995,889,723'Standby voltage boosting stage and method for a memory device'19995,886,945'Circuit and method to adjust memory timing'19995,881,001'Data sensing timing modulating circuit, particularly for non-volatile memories'19995,878,049'Circuits and methods for read-enabling memory devices synchronously with the reaching of the minimum functionality conditions of the memory cells and reading circuits, particularly for non-volatile memories'19995,867,504'Semiconductor memory device with row and column redundancy circuits and a time-shared redundancy circuit test architecture.'19995,864,503'Method for verifying electrically programmable non-volatile memory cells of an electrically programmable non-volatile memory device after programming'19995,864,513'System for determining the programmed/non programmed status of A memory cell'19995,864,562'Circuit for transferring redundancy data of a redundancy circuit inside a memory device by means of a time-shared approach'19995,864,500'Auto-saving circuit for programming configuration elements in non-volatile memory devices'19995,859,810'Pulse generation circuit and method for synchronized data loading in an output pre-buffer'19995,854,762'Protection circuit for redundancy register set-up cells of electrically programmable non-volatile memory devices'19985,854,770'Decoding hierarchical architecture for high integration memories'19985,850,361'Programmable memory with single bit encoding'19985,847,584'Threshold detecting device'19985,844,851'Anti-noise and auto-stand-by memory architecture'19985,841,728'Hierarchic memory device having auxiliary lines connected to word lines'19985,838,623'Method for detecting redunded defective addresses in a memory device with redundancy'19985,838,619'Method and apparatus for redundancy management of non-volatile memories'19985,831,915'Memory device with clocked column redundancy'19985,831,891'Non-volatile memory device having optimized management of data transmission lines'19985,821,788'Zero consumption power-on-reset'19985,821,806'Boost regulator'19985,815,437'Data input/output managing device, particularly for a non-volatile memory'19985,815,457'Bit line selection decoder for an electronic memory'19985,812,467'Redundancy memory register'19985,805,435'Voltage booster for memory devices'19985,801,988'Circuit for the generation of a voltage as a function of the conductivity of an elementary cell of a non-volatile memory'19985,793,699'Circuit for the generation and reset of timing signal used for reading a memory device'19985,777,941'Column multiplexer'19985,768,115'Voltage booster with an acceleration circuit'19985,764,570'Current detecting circuit'19985,760,497'Charge pump circuit with multiple boost stages'19985,754,473'Circuit for the switching of supply voltages in electrically programmable and cancelable non-volatile semiconductor memory devices'19985,754,483'Reference word line and data propagation reproduction circuit for memories provided with hierarchical decoders'19985,751,654'Driver device for selection lines for a multiplexer, to be used in a wide range of supply voltages, particularly for non-volatile memories'19985,742,187'Decoder with reduced architecture'19985,737,268'Modulated slope signal generation circuit, particularly for latch data sensing arrangements'19985,734,610'Circuit for reading non-volatile memories'19985,731,716'Programmable multibit register for coincidence and jump operations and coincidence fuse cell'19985,717,642'Load signal generating method and circuit for nonvolatile memories'19985,708,601'Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device'19985,708,604'Dynamic selection control in a memory'19985,687,124'Circuit for identifying a memory cell having erroneous data stored therein'19975,663,921'Internal timing method and circuit for programmable memories'19975,659,498'Unbalanced latch and fuse circuit including the same'19975,657,276'Output stage for integrated circuits, particularly for electronic memories'19975,650,671'Charge pump circuit'19975,644,529'Integrated circuit for the programming of a memory cell in a non-volatile memory register'19975,633,834'Synchronization device for output stages, particularly for electronic memories'19975,602,786'Method for programming redundancy registers in a column redundancy integrated circuitry for a semiconductor memory device, and column redundancy integrated circuitry'19975,566,114'Redundancy circuitry for a semiconductor memory device'19965,563,826'Memory array cell reading circuit with extra current branch'19965,559,449'Programmable logic array structure for semiconductor nonvolatile memories, particularly flash-eeproms'19965,559,743'Redundancy circuitry layout for a semiconductor memory device'19965,548,554'Integrated programming circuitry for an electrically programmable semiconductor memory device with redundancy'19965,541,884'Method and circuit for suppressing data loading noise in nonvolatile memories'19965,532,972'Method and circuit for timing the reading of nonvolatile memories'19965,515,332'Method and circuit for timing the loading of nonvolatile-memory output data'19965,499,217'Bias circuit for a memory line decoder driver of nonvolatile memories'19965,493,531'Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device'1996RE035121'Regulation of the output voltage of a voltage multiplier'19955,469,389'Semiconductor memory with memory matrix comprising redundancy cell columns associated with single matrix sectors'19955,461,713'Current offset sense amplifier of a modulated current or current unbalance type for programmable memories'19955,408,148'Sense amplifier for programmable memories with a virtually enhanced source of signal'19955,404,334'Anti-noise and auto-stand-by memory architecture'19955,355,333'Dynamic reference system for sense amplifier'19945,347,493'Row decoder for NAND-type ROM'19945,327,379'Current offset sense amplifier of a modulated current or current unbalance type for programmable memories'19945,321,317'Zero-consumption power-on reset circuit'19945,282,169'Compensated sense circuit for storage devices'19945,276,644'Sense circuit for storage devices such as non-volatile memories, with compensated offset current'19945,270,590'Sense circuit for storage devices such a non-volatile memories, with enhanced sensing discrimination'19935,218,570'Sense circuit for reading data stored in nonvolatile memory cells'19935,097,226'Voltage-boosted phase oscillator for driving a voltage multiplier'19924,956,569'CMOS logic circuit for high voltage operation'19904,933,827'Regulation of the output voltage of a voltage multiplier'19904,922,402'CMOS voltage multiplier'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–2002Patents assigned to SGS THOMSON MICROELECTRONICS (73)· patent assignee history
1990–2020Based in Sesto San Giovanni, IT· patent location history
1994–2011Patents assigned to ST MICROELECTRONICS SRL (67)· patent assignee history
1994–2006Based in Milan, IT· patent location history
1994–1997Based in Luserna San Giovanni, IT· patent location history
1998Based in Giovanni, IT· patent location history
2009–2014Patents assigned to PASCUCCI LUIGI (6)· patent assignee history
2009–2014Patents assigned to ROLANDI PAOLO (6)· patent assignee history
2014–2020Patents assigned to MICRON TECHNOLOGY INC (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SGS THOMSON MICROELECTRONICS | 73 | 1990–2002 |
| ST MICROELECTRONICS SRL | 67 | 1994–2011 |
| MICRON TECHNOLOGY INC | 7 | 2014–2020 |
| PASCUCCI LUIGIself | 6 | 2009–2014 |
| ROLANDI PAOLO | 6 | 2009–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sesto San Giovanni, IT | 136 | 1990–2020 |
| Milan, IT | 9 | 1994–2006 |
| Giovanni, IT | 4 | 1998 |
| Luserna San Giovanni, IT | 4 | 1994–1997 |