Twin well methods of forming CMOS integrated circuitry

This invention relates to twin well methods of forming CMOS integrated circuitry.

Typical CMOS circuitry fabrication includes several major process operations, with each operation requiring several steps and sub-steps. In each sub-step, several events could result in defective CMOS transistors, for example, substrate breakage, substrate warping, process variation, process defects and masking defects. The higher the number of sub-steps or steps, the higher the potential that a semiconductor substrate will not result with operable circuitry. Accordingly, the semiconductor processing industry is continually striving to reduce the number of processing steps, including masking steps.

CMOS circuitry includes PMOS transistor devices and NMOS transistor devices formed proximate each other over a semiconductor substrate. A component of each device includes a well structure in the semiconductor substrate. The PMOS devices are formed in n-wells while NMOS devices are formed in p-wells. One conventional method for forming the wells is a “twin-well” method. A semiconductor substrate is cut from an ingot and provided by a silicon ingot supplier. Typically, the semiconductor substrate received is p− doped.

Two separate masking steps provide the p-well and n-well within the p− doped substrate. The substrate is initially masked so that one of the desired p-well or n-well regions is masked while the other is unmasked. The desired implant is then conducted into the unmasked region to form the desired well. The process is then reversed with the just implanted region masked, and the other region unmasked and subjected to the opposite type dopant implant.

The transistor gates are typically formed after the well implants previously described and includes all the gate structures to be heavily n+ doped polysilicon for both the PMOS and NMOS devices. However, high performance CMOS devices, such as SRAMs and EDRAMs, may include p-type polysilicon gates for the PMOS devices and n-type polysilicon gates for the NMOS devices. To provide these gate structure designs, two masking steps are performed. One is for the p-type implant for the PMOS devices and one is for the n-type implant for the NMOS devices. Combine these two masking steps with the two masking steps previously discussed for “twin-well” formation and at least four masking steps are performed to implant the wells and gates during CMOS transistor fabrication.

Furthermore, each masking step has inherent and unique problems, particularly alignment accuracy during application of masking material. If the masking material is not aligned properly, one conductivity material in the PMOS devices may overlap another conductivity material in the NMOS devices effectively rendering the devices useless. For example, the p-type polysilicon gate for the PMOS device and n-type polysilicon gate for the NMOS device previously discussed are in such close proximity that the masking steps poses process limitations for CMOS fabrication. As the spacing between the PMOS and NMOS devices diminishes, alignment tolerances decrease thereby increasing the difficulty of aligning the masking material.

In accordance with an aspect of the invention, a twin-well method of forming CMOS integrated circuitry having first and second conductivity type gates includes conducting a first conductivity type well implant, a second conductivity type well implant, a first conductivity type gate implant and a second conductivity type gate implant using no more than two masking steps.

In another aspect of the invention, a twin well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates includes conducting a first conductivity type well implant and a second conductivity type gate implant in a common masking step.

In yet another aspect of the invention, a twin well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates includes depositing a transistor gate layer of a semiconductive material over a semiconductor substrate. After depositing the transistor gate layer and in one masking step, effectively masking a first substrate area configured for formation of first conductivity type transistors while leaving a second substrate area configured for formation of second conductivity type transistors effectively unmasked. In the one masking step, a first conductivity type well implant is conducted into the second substrate area and a second conductivity type gate implant is conducted into the transistor gate layer within the second substrate area. In another masking step after the one masking step, the second substrate area is effectively masked by a masking material and only a portion of the first substrate area is effectively masked while leaving a majority of the first substrate area effectively unmasked. With the masking material in place, a first conductivity type implant is conducted into the transistor gate layer within the first substrate area while leaving a substantially undoped region of transistor gate layer semiconductive material within the first substrate area. After conducting the first conductivity type implant into the transistor gate layer within the first substrate area, at least some of the masking material within the first substrate area is laterally etched away. After laterally etching away the masking material within the first substrate area, a second conductivity type well implant is conducted within the first substrate area.

Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

FIG. 1 is a fragmentary sectional view of a semiconductor substrate at one processing step in accordance with one embodiment of the invention.

FIG. 2 is a view of the FIG. 1 substrate fragment at a processing step subsequent to that shown in FIG. 1 .

FIG. 3 is a view of the FIG. 1 substrate fragment at a processing step subsequent to that shown in FIG. 2 .

FIG. 4 is a view of the FIG. 1 substrate fragment at a processing step subsequent to that shown in FIG. 3 .

FIG. 5 is a view of the FIG. 1 substrate fragment at a processing step subsequent to that shown in FIG. 4 .

FIG. 6 is a view of the FIG. 1 substrate fragment at a processing step subsequent to that shown in FIG. 5 .

FIG. 7 is a view of the FIG. 1 substrate fragment at a processing step subsequent to that shown in FIG. 6 .

FIG. 8 is a fragmentary sectional view of a semiconductor substrate at one processing step in accordance with another embodiment of the invention.

FIG. 9 is a view of the FIG. 8 substrate fragment at a processing step subsequent to that shown in FIG. 8 .

FIG. 10 is a view of the FIG. 8 substrate fragment at a processing step subsequent to that shown in FIG. 9 .

FIG. 11 is a view of the FIG. 8 substrate fragment at a processing step subsequent to that shown in FIG. 10 .

This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).

To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.

With reference to FIGS. 1-7, an embodiment of the method of the present invention is illustrated. This embodiment encompasses a twin-well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates (i.e., p and n type, or n and p type). Referring to FIG. 1, a semiconductor substrate in process is indicated generally by reference numeral 10 . A first substrate area 14 is configured for formation of first conductivity type transistors and a second substrate area 12 is configured for formation of second conductivity type transistors. The semiconductor fragment 10 comprises bulk substrate material 20 , for example, monocrystalline silicon. The semiconductor substrate 10 comprises isolation regions 22 formed therein and a gate dielectric layer 24 formed thereon. An exemplary dielectric layer 24 comprises silicon dioxide. A transistor gate layer 26 comprising a semiconductor material is formed over the semiconductor substrate 10 . An exemplary semiconductor material comprises polysilicon.

Referring to FIG. 2, after forming the transistor gate layer, a first masking material 28 (i.e., photoresist) masks the first substrate area 14 while leaving the second substrate area 12 unmasked. In one masking step, a first conductivity type well implant 30 is conducted into the second substrate area 12 to form first conductivity type well 32 . Referring to FIG. 3, in the one masking step, exemplary implants 40 may be conducted, for example, punch-through implants 46 and channel enhancement implants 44 .

Referring to FIG. 4, in the one masking step, a second conductivity type gate implant 50 is conducted into the transistor gate layer 26 within the second substrate area 14 .

Referring to FIG. 5, the first masking material 28 is removed from the first substrate area 14 and the second substrate area 12 is masked with another masking material 72 (i.e., photoresist). In the shown embodiment, various implants are indicated generally by reference numeral 70 . While the second substrate area 12 is masked with masking material 72 , a first conductivity type gate implant is conducted into the transistor gate layer 26 within the first substrate area 14 and a second conductivity type well implant into the first substrate area 14 to form second conductivity type well 74 . While the second substrate area 12 is masked, other exemplary implants may be conducted, for example, punch-through implants 46 and channel enhancement implants 44 .

Referring to FIG. 6, the second masking material 72 is removed from the second substrate area 12 . A layer 62 comprising one or any combination of elemental metals, metal alloys, metal silicides, and metal nitrides is formed over transistor gate layer 26 . An insulative layer 64 is formed over layer 62 . An exemplary insulative layer 64 comprises silicon dioxide deposited by a TEOS source, or alternatively Si 3 N 4 .

Referring to FIG. 7, transistor gates 69 are formed over the first and second substrate areas 14 / 12 from the transistor gate layer 26 , layer 62 and insulative layer 64 . Insulative spacers 68 can be formed adjacent transistor gates 69 . Source/drain regions 42 are formed proximate the transistor gates 69 in the first and second substrate areas 14 / 12 . In accordance with one aspect of the invention, in any one common masking step, the well implants, gate implants, channel enhancement implants and punch-through implants disclosed in FIGS. 1-7 can be conducted in any order and in any combination, as might be selected or optimized by the designer.

With reference to FIGS. 8-11, a second embodiment of the method of the present invention is illustrated. Like numerals from the first described embodiment are employed where appropriate, with differences being indicated with the suffix (a) or with different numerals.

Referring to FIG. 8, in one masking step, the first substrate area 14 is masked by first masking material 28 while leaving the second substrate area 12 effectively unmasked. In the one masking step, implants 60 include a first conductivity type well implant conducted into the second substrate area 12 to form first conductivity type well 32 and a second conductivity type gate implant conducted into the transistor gate layer 26 within the second substrate area 12 . Additional exemplary implants may be conducted, such as, punch-through implants 46 and channel enhancement implants 44 . In accordance with an aspect of the invention, in this one common masking step, the well implants, gate implants, channel enhancement implants and punch-through implants can be conducted in any order and in any combination.

Referring to FIG. 9, the first masking material 28 is removed from the first substrate area 14 and in another masking step after the one masking step, the second substrate area 12 and only a portion of the first substrate area 14 proximate the second substrate area 12 are masked with a second masking material 81 while leaving a majority of the first substrate area 14 effectively unmasked. With the second masking material 81 in place, a first conductivity type gate implant 80 is conducted into the transistor gate layer 26 within the first substrate area 14 leaving a substantially undoped region 82 of transistor gate layer semiconductor material within the first substrate area 12 proximate the second conductivity type gate implant into the transistor gate layer 26 . In the context of this document, “substantially undoped region” defines a region having 10 16 atoms/cm 3 of dopant concentration.

Referring to FIG. 10, after the first conductivity type gate implant 80 is conducted into. the transistor gate layer 26 within the first substrate 14 , at least some of the second masking material 81 is laterally etched away to remove it from being received within the first substrate area 14 while leaving the second substrate area 12 effectively covered. An exemplary laterally etching comprises an isotropic etching, for example, a photoresist descum etching. Exemplary descum etching processes comprise exposing semiconductor substrate 10 to any one of the three following environments. A first environment includes a temperature at about 90° C., 1.5 Torr, for approximately one minute, in O 2 at 2100 sccm. A second environment includes a temperature at about 90° C., 1.5 Torr, for a time range of 10 seconds to 10 minutes, in O 2 at a range of 200 to 2100 sccm. The slower the O 2 flow the slower the etch rate of the masking material. Accordingly, one can selectively control the etching process of second masking material 81 to any desired dimensions. A third environment includes a temperature at about 90° C., 1.5 Torr, for approximately 125 minutes, in O 2 at 2100 sccm and 2000 W microwave power. A second exemplary isotropic etching comprises an in situ process in an etch chamber exposing semiconductor substrate 10 to a CF 4 and/or CHF 3 based plasma at a power of approximately 200 W for a time range of from 2 to 25 seconds.

After the isotropic etching, a second conductivity type well implant 90 is conducted within the first substrate area 14 . Additional exemplary implants may be conducted, for example, punch-through implants 46 and channel enhancement implants 44 .

Referring to FIG. 11, the second masking material 81 is removed from the second substrate area 12 and transistor gates 69 are formed over the first and second substrate areas 14 / 12 from the transistor gate layer 26 . After forming the transistor gates 69 , source/drain regions 42 are formed proximate the transistor gates 69 in the first and second substrate areas 14 / 12 .

A preferred goal in the second embodiment is independent control of the spacing between the gate implants and the well implants. By controlling the amount of second masking material 81 formed over the first substrate area 14 proximate the second substrate area 12 , the dimensions of undoped region 82 can be controlled. Accordingly, the spacing between the first conductivity type gate implant and the second conductivity type gate implant can be controlled. Additionally, by selectively controlling the etching process of second masking material 81 , the dimensions of the subsequent well implant can be controlled. Accordingly, the spacing between the first conductivity type well implant and the second conductivity type well implant can be controlled. Independently controlling the spacing between well implants and between gate implants eases the tolerance parameters of any given masking step. Consequently, the fabrication of CMOS devices with smaller dimensions is possible because masking process constraints are diminished with the increased tolerances.

Further in accordance with an aspect of the invention, all the implants are collectively conducted using two masking steps. An exemplary masking material for any one, or all, the masking steps comprises photoresist. Still further in accordance with the invention, the first conductivity type comprises n and the second conductivity type comprises p. Alternatively, the first conductivity type comprises p and the second conductivity type comprises n. Moreover, as shown in the embodiments, the first substrate area 14 can be masked first; however, the second substrate area 12 can be masked first.

In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.