Inventor

Zhongze Wang

Inventor

San Diego, CA, US

Overview

2000–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 110 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices25%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%

G11CStatic stores14%

H01LSemiconductor devices12%

H10BElectronic memory devices12%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%

G06FElectric digital data processing3%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%

H03KPulse technique1%

PatentTitleYear

10,777,259Static random-access memory (SRAM) for in-memory computing2020 10,290,352System, apparatus, and method of programming a one-time programmable memory circuit having dual programming regions2019 10,194,529Partial metal fill for preventing extreme-low-k dielectric delamination2019 10,141,317Metal layers for a three-port bit cell2018 10,037,795Seven-transistor static random-access memory bitcell with reduced read disturbance2018 9,941,154Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device2018 9,876,017Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells2018 9,876,123Non-volatile one-time programmable memory device2018 9,875,788Low-power 5T SRAM with improved stability and reduced bitcell size2018 9,865,330'Stable SRAM bitcell design utilizing independent gate FinFET'2018 9,842,802'Integrated circuit device featuring an antifuse and method of making same'2017 9,812,188'Static random-access memory (SRAM) sensor for bias temperature instability'2017 9,806,083'Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance, and related methods'2017 9,786,356'Memory device with adaptive voltage scaling based on error information'2017 9,773,567'Reduced silicon-oxide-nitride-oxide-silicon (SONOS) flash memory program disturb'2017 9,691,868'Merging lithography processes for gate patterning'2017 9,666,481'Reduced height M1 metal lines for local on-chip routing'2017 9,576,801'High dielectric constant/metal gate (HK/MG) compatible floating gate (FG)/ferroelectric dipole non-volatile memory'2017 9,564,361'Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device'2017 9,536,596'Three-port bit cell having increased width'2017 9,524,972'Metal layers for a three-port bit cell'2016 9,508,589'Conductive layer routing'2016 9,508,439'Non-volatile multiple time programmable memory device'2016 9,502,424'Integrated circuit device featuring an antifuse and method of making same'2016 9,496,048'Differential one-time-programmable (OTP) memory array'2016 9,495,503'Method and apparatus to enable a selective push process during manufacturing to improve performance of a selected circuit of an integrated circuit'2016 9,478,490'Capacitor from second level middle-of-line layer in combination with decoupling capacitors'2016 9,461,055'Advanced metal-nitride-oxide-silicon multiple-time programmable memory'2016 9,460,777'SRAM read buffer with reduced sensing delay and improved sensing margin'2016 9,455,026'Shared global read and write word lines'2016 9,449,709'Volatile memory and one-time program (OTP) compatible memory cell and programming method'2016 9,431,097'Volatile/non-volatile SRAM device'2016 9,424,909'Static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation'2016 9,413,349'High-K (HK)/metal gate (MG) (HK/MG) multi-time programmable (MTP) switching devices, and related systems and methods'2016 9,396,931'Method of forming fins from different materials on a substrate'2016 9,378,803'System and method to regulate operating voltage of a memory array'2016 9,379,058'Grounding dummy gate in scaled layout design'2016 9,373,387'Static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation'2016 9,349,686'Reduced height M1 metal lines for local on-chip routing'2016 9,336,864'Silicon germanium read port for a static random access memory register file'2016 9,336,863'Dual write wordline memory cell'2016 9,318,564'High density static random access memory array having advanced metal patterning'2016 9,263,279'Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern features'2016 9,257,407'Heterogeneous channel material integration into wafer'2016 9,196,583'Via material selection and processing'2015 9,111,635'Static random access memories (SRAM) with read-preferred cell structures, write drivers, related systems, and methods'2015 9,047,960'Flash memory cell with capacitive coupling between a metal floating gate and a metal control gate'2015 8,975,724'Anti-fuse device'2015 8,969,166'Method and apparatus for selectively improving integrated device performance'2015 8,799,847'Methods for designing fin-based field effect transistors (FinFETS)'2014 8,658,506'Method and apparatus for selectively improving integrated device performance'2014 8,623,748'Method of forming a semiconductor structure'2014 8,558,320'Systems and methods employing a physically asymmetric semiconductor device having symmetrical electrical behavior'2013 8,279,693'Programmable tracking circuit for tracking semiconductor memory read current'2012 8,194,478'Systems and methods for writing to multiple port memory circuits'2012 8,120,109'Low dose super deep source/drain implant'2012 7,968,954'Intermediate semiconductor device having nitrogen concentration profile'2011 7,872,930'Testing a memory device having field effect transistors subject to threshold voltage shifts caused by bias temperature instability'2011 7,816,246'Methods of making semiconductor fuses'2010 7,314,812'Method for reducing the effective thickness of gate oxides by nitrogen implantation and anneal'2008 7,259,435'Intermediate semiconductor device having nitrogen concentration profile'2007 7,169,662'Methods for making semiconductor structures having high-speed areas and high-density areas'2007 7,153,731'Method of forming a field effect transistor with halo implant regions'2006 7,154,146'Dielectric plug in mosfets to suppress short-channel effects'2006 7,119,369'FET having epitaxial silicon growth'2006 7,112,482'Method of forming a field effect transistor'2006 7,109,105'Methods of making semiconductor fuses'2006 7,095,083'Methods for making semiconductor structures having high-speed areas and high-density areas'2006 7,012,293'Fabricating an SRAM cell'2006 6,987,291'Integrated transistor circuitry'2006 6,984,570'Wafer bonding method of forming silicon-on-insulator comprising integrated circuitry'2006 6,977,419'MOSFETs including a dielectric plug to suppress short-channel effects'2005 6,974,757'Method of forming silicon-on-insulator comprising integrated circuitry'2005 6,962,841'Suppression of cross diffusion and gate depletion'2005 6,949,479'Methods of forming transistor devices'2005 6,936,894'Silicon-on-insulator comprising integrated circuitry'2005 6,930,029'Method of passivating an oxide surface subjected to a conductive material anneal'2005 6,927,473'Semiconductor fuses and semiconductor devices containing the same'2005 6,903,420'Silicon-on-insulator comprising integrated circuitry'2005 6,900,494'Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same'2005 6,872,660'Methods of forming conductive contacts'2005 6,867,131'Apparatus and method of increasing sram cell capacitance with metal fill'2005 6,864,155'Methods of forming silicon-on-insulator comprising integrated circuitry, and wafer bonding methods of forming silicon-on-insulator comprising integrated circuitry'2005 6,812,103'Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects'2004 6,812,529'Suppression of cross diffusion and gate depletion'2004 6,808,994'Transistor structures and processes for forming same'2004 6,806,134'Sidewall strap for complementary semiconductor structures and method of making same'2004 6,784,062'Transistor formation for semiconductor devices'2004 6,774,022'Method of passivating an oxide surface subjected to a conductive material anneal'2004 6,770,921'Sidewall strap for complementary semiconductor structures and method of making same'2004 6,767,778'Low dose super deep source/drain implant'2004 6,744,102'MOS transistors with nitrogen in the gate oxide of the p-channel transistor'2004 6,730,553'Methods for making semiconductor structures having high-speed areas and high-density areas'2004 6,723,597'Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same'2004 6,716,687'FET having epitaxial silicon growth'2004 6,703,263'Semiconductor fuses, methods of using the same, methods of making the same, and semiconductor devices containing the same'2004 6,673,715'Methods of forming conductive contacts'2004 6,613,617'Cross-diffusion resistant dual-polycide semiconductor structure and method'2003 6,599,789'Method of forming a field effect transistor'2003 6,583,518'Cross-diffusion resistant dual-polycide semiconductor structure and method'2003 6,559,053'Method of passivating an oxide surface subjected to a conductive material anneal'2003 6,555,455'Methods of passivating an oxide surface subjected to a conductive material anneal'2003 6,548,383'Twin well methods of forming CMOS integrated circuitry'2003 6,541,395'Semiconductor processing method of forming field effect transistors'2003 6,511,868'Semiconductor fuses, methods of using the same, methods of making the same, and semiconductor devices containing the same'2003 6,503,805'Channel implant through gate polysilicon'2003 6,417,546'P-type FET in a CMOS with nitrogen atoms in the gate dielectric'2002 6,277,674'Semiconductor fuses, methods of using the same, methods of making the same, and semiconductor devices containing the same'2001 6,162,693'Channel implant through gate polysilicon'2000 6,093,661'Integrated circuitry and semiconductor processing method of forming field effect transistors'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2014Patents assigned to MICRON TECHNOLOGY INC (54)· patent assignee history

2000–2014Based in Boise, ID, US· patent location history

2011–2020Patents assigned to QUALCOMM INC (54)· patent assignee history

2011–2020Based in San Diego, CA, US· patent location history

2012–2018Patents assigned to WANG ZHONGZE (10)· patent assignee history

2013–2018Patents assigned to HAN BEOM-MO (2)· patent assignee history

2018Patents assigned to GE LIXIN (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	54	2000–2014
QUALCOMM INC	54	2011–2020
WANG ZHONGZEself	10	2012–2018
GE LIXIN	2	2018
HAN BEOM-MO	2	2013–2018

Locations

Location	Patents	Span
San Diego, California, US	55	2011–2020
Boise, ID, US	55	2000–2014