USPatent applicationPatented

Leaded semiconductor device package for use in nonsoldering assembling

Granted 28 May 2002 · 3 office actions

Current assignee: General Semiconductor, Inc. · originally William John Nelson

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Inventors: Alice Tseng, William John Nelson, Stanley Lai, K. R. Lee · Examiner: Dean A. Reichard · AU 2831 · TC 2800

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13 dated events
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Abstract

A leaded semiconductor device package for nonsoldering assembling is disclosed. In the package of the invention, both leads of a semiconductor device package are flattened, cut and bent by automatic machines on the bais of conventional packaging process. Unlike a conventional semiconductor device package which is electrically connected to a circuit by soldering, the flattened and bent parts of both leads of the semiconductor device package can be electrically connected to a circuit by elastically contacting and directly assembling without soldering.

Description

4 parts
›BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a leaded semiconductor device package, and in particular to a package in which semiconductor device leads are processed to be adapted to nonsoldering assembling.

2. Description of the Related Art

Both leads of a conventional semiconductor device package with, for example, a specification of DO-41, are electrically connected to a circuit by soldering. However, under a circumstance where soldering equipment cannot be provided or used, a semiconductor device package having leads which can be electrically connected to a circuit without soldering would be required. If a leaded semiconductor device package made for nonsoldering assembling is provided, it would be an innovative addition to conventional semiconductor device packages which are made by soldering leads.

›SUMMARY OF THE INVENTION

In view of the above, the first object of the invention is to provide a semiconductor device lead package made for nonsoldering assembling. In the package, both leads of conventional semiconductor device package are partially flattened, cut and bent so as to be connected to a circuit without soldering.

The second object of the invention is to provide a leaded semiconductor device package made for nonsoldering, assembling by originally existing equipment. Therefore, original resources can be utilized effectively and investments in new equipment can be greatly reduced.

›BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus do not limit the present invention, and wherein:

FIG. 1 is a schematic view showing a conventional semiconductor device package;

FIG. 2 is a schematic view showing the steps of flattening, cutting and bending semiconductor device package leads of the present invention;

FIG. 3 is a side view showing a semiconductor device package having non-soldered leads according to the invention; and

FIG. 4 is a semiconductor device package according to the invention which is assembled on a circuit.

›DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a conventional semiconductor device package 10 with a specification of DO-41. The conventional semiconductor device package 10 has a length in the range of 4.06 mm-5.21 mm and a diameter in the range of 2.03-2.72 mm. Two leads 15 on both sides of the semiconductor device package 10 each has a length of approximately 27.94 mm and a diameter in the range of 0.71-0.86 mm.

FIG. 2 is a schematic view showing the steps of processing conventional semiconductor device package leads by an automatic machine. In the steps, part of one lead 15 adjacent to the semiconductor device package 10 is first flattened, and then part of the other lead 15 ′ adjacent to the semiconductor device package 10 is flattened. The remaining parts of the two leads 15 and 15 ′ which are not flattened, are cut off. Next, the flattened parts of the two leads 15 and 15 ′ are bent. The above-stated two-stage flattening step (one stage is to flatten one lead and the other stage is to flatten the other lead) can prevent internal component of the semiconductor device package 10 from damage. FIG. 3 is a side view showing a semiconductor device package 35 having non-soldered leads 30 and 30 ′ according to the invention. The length of leads 30 and 30 ′ have been trimmed to be at the same level with the periphery of the side surfaces 38 and 38 ′ of the semiconductor device package 35 . Furthermore, there is a small angle formed between each bent lead 30 and a corresponding side surface of the semiconductor device package 35 for a better elastic contact with a circuit.

FIG. 4 is a semiconductor device package according to the invention assembled to a circuit 48 . As shown in FIG. 4, the semiconductor device package 35 is mounted on a carrier 44 , wherein the two flattened and bent leads 30 and 30 ′ are elastically engaged with two copper plates 42 respectively. The semiconductor device package 35 is electrically connected to the circuit 48 via the two copper plates 42 and a wire 46 . Furthermore, as can be seen from FIG. 4, there is a small angle formed between each of the flattened and bent leads 30 , 30 ′ and corresponding side surfaces 38 , 38 ′ of the semiconductor device package 35 respectively for a better elastic contact with the copper plates 42 .

While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded in the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims as granted

4 claims

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Classifications

7 codes
IPC · International Patent Classification
Section H — Electricity
  • H05K3/30
  • H01L21/48
  • H10W70/40
USPC · US Patent Classification
174/52.4257/696257/694439/70

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File wrapper

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Pendency
3.5 y
1,264 days filing → grant
Office actions
3
non-final + final
Responses
3
no RCE
Examiner
Dean A. Reichard
art unit 2831 · TC 2800
Citations: 8 back · 1 forward

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Documents

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Chain of title

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